Page 1 FUJITSU SEMICONDUCTOR CM44-10129-1E CONTROLLER MANUAL -16LX 16-bit Microcontroller MB90330 series HARDWARE MANUAL...
Page 3 -16LX 16-bit Microcontroller MB90330 series HARDWARE MANUAL FUJITSU LIMITED...
Page 5 MB90330 Series. Please read through this manual. For more information on various instructions, refer to "Instruction Manual". Trademarks MC, an abbreviation for, FUJITSU Flexible Microcontroller and is a registered trademark of FUJITSU LIMITED. Embedded Algorithm is a registered trademark of Advanced Micro Devices, Inc.
Page 6 oscillation stability wait time. Chapter 6 Low-Power Consumption Mode This chapter describes the overview of the low-power consumption mode, register configuration/ function, and operation of the low-power consumption mode. Chapter 7 Mode setting This chapter describes the overview of mode settings, mode pin, mode data, and operation in each mode of mode setting.
Page 7 Chapter 26 Example of connecting serial writing This chapter describes the serial on-board writing of the flash ROM (Fujitsu standard). APPENDIX Appendix includes detailed information on I/O map, interrupt vector, and instruction list, which are not...
Page 8 (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.
Page 9: Table Of Contents
CONTENTS CHAPTER 1 OVERVIEW .....................1 Feature of MB90330 Series........................2 Block Diagram ............................7 Package Dimension..........................8 Pin Assignment............................10 Pin Function............................11 I/O Circuit Types ............................18 Handling of Device..........................21 CHAPTER 2 CPU .......................25 Outline Specification of CPU .........................26 Memory Space............................27 Register of CPU.............................32 2.3.1 Accumulator (A)..........................34 2.3.2 User Stack Pointer (USP) and System Stack Pointer (SSP) ............35...
Page 10 Register of µDMAC.......................... 89 3.8.2 3.8.2.1 DMA Descriptor Channel Specification Register (DCSR) ............90 3.8.2.2 DMA Status Register (DSRH/DSRL).................... 92 3.8.2.3 DMA Stop Status Register (DSSR) ....................93 3.8.2.4 DMA Permission Register (DERH/DERL) ..................94 3.8.3 DMA Descriptor Window Register (DDWR)..................95 3.8.3.1 DMA Data Counter (DDCTH/DDCTL) ..................
Page 11 Mode Data ............................178 External Memory Access ........................182 7.4.1 Automatic Ready Function Selection Register (ARSR)..............184 7.4.2 External Address Output Control Register (HACR)................185 7.4.3 Bus Control Signal Selection Register (EPCR) ................186 Operation in Each Mode of Mode Setting....................188 7.5.1 External Memory Access Control Signal ..................189 7.5.2 Ready Function ..........................192 7.5.3...
Page 12 12.3.3 Operation of 16-bit Input Capture ....................260 12.3.4 Timing of 16-bit Free-run Timer ..................... 261 12.3.5 Output Compare Timing ........................ 262 12.3.6 Input Timing of Input Capture ......................263 CHAPTER 13 USB FUNCTION ..................265 13.1 Overview of USB Function........................266 13.2 Block Diagram of USB Function ......................
Page 13 14.5.8 Error Status ............................347 14.5.9 Packet End .............................348 14.5.10 Suspend Resume ...........................349 14.5.11 Cutting of Device ..........................352 14.6 Each Token Flow Chart of USB Mini-HOST ..................353 CHAPTER 15 PWC TIMER ....................355 15.1 Overview of PWC Timer ........................356 15.2 Register of PWC Timer........................358 15.2.1 PWC Control Status Register (PWCSR) ..................359 15.2.2 PWC Data Buffer Register (PWCR) ....................364 15.2.3 PWC Ratio of Dividing Frequency Control Register (DIVR) ............365...
Page 14 18.4 Precaution of Using DTP/External Interrupt..................427 CHAPTER 19 8/10-BIT A/D CONVERTER................429 19.1 Overview of 8/10-bit A/D Converter ....................430 19.2 Configuration of 8/10-bit A/D Converter....................431 19.3 Register of 8/10-bit A/D Converter...................... 433 19.3.1 A/D Control Status Register (High) (ADCS1)................. 434 19.3.2 A/D Control Status Register (Low) (ADCS0) .................
Page 15 21.6.1 Baud Rate of the UART Internal Clock Using the Dedicated Baud Rate Generator ......501 21.6.2 Baud Rate of the External Clock Using the Dedicated Baud Rate Generator ........502 21.6.3 Baud Rate of the External Clock (One-to-one Mode)..............503 21.7 Explanation of Operation of UART ......................504 21.7.1 Operation in Asynchronous Mode (Operation Mode 0 or Operation Mode1) .........506 21.7.2 Operation in Synchronous Mode (Operation Mode 2)..............509 21.7.3 Bidirectional Communication Function (Normal Mode) ..............512...
Page 16 25.6 Write/Erase of Flash memory ......................577 25.6.1 Read/Reset State in Flash Memory ....................578 25.6.2 Writing Data to Flash Memory ....................... 579 25.6.3 Erasing All Data from Flash Memory (Chip Erase) ................ 581 25.6.4 Erasing Any Data in Flash Memory (Sector Erasing) ..............582 25.6.5 Flash Memory Sector Erase Suspension..................
Page 17: Chapter 1 Overview
CHAPTER 1 OVERVIEW This chapter describes basics to give the understanding of the MB90330 series as a whole such as the features, block diagrams, and overviews of the functions. 1.1 Feature of MB90330 Series 1.2 Block Diagram 1.3 Package Dimension 1.4 Pin Assignment 1.5 Pin Function 1.6 I/O Circuit Types...
Page 18: Feature Of Mb90330 Series
CHAPTER 1 OVERVIEW Feature of MB90330 Series The MB90330 series are 16-bit microcontrollers designed for applications, such as personal computer peripheral devices, that require USB communications. The USB function enables not only 12-Mbps function operations but also simplified host operations (Mini-HOST). It is equipped with functions that are suitable for personal computer peripheral devices such as displays and audio devices, and control of mobile devices that support USB communications.
Page 19 CHAPTER 1 OVERVIEW Capacity of built-in ROM and ROM type • Mask ROM:256 Kbytes, 384 Kbytes • Flash ROM:384 Kbytes Built-in RAM • Mass production products:16 Kbytes, 24 Kbytes • Flash products:24 Kbytes • Evaluation chip: 28 Kbytes Process: CMOS technology Low-power consumption (standby) mode •...
Page 20 CHAPTER 1 OVERVIEW C interface: 3 channels 8/10-bit A/D converter (RC sequential comparator type):16 channels DTP/external interrupt: 8 channels • USB function (Conform to USB2.0 Full Speed):1 channel • USB Mini-HOST:1 channel...
Page 21 CHAPTER 1 OVERVIEW Product Lineup Table 1.1-1 MB90330 Series Product Lineup List (1/2) Product name MB90V330A * MB90F334A MB90333A MB90334A Classification For evaluation Flash products MASK ROM products ROM size None 384 Kbytes 256 Kbytes 384 Kbytes RAM size 28 Kbytes 24 Kbytes 16 Kbytes 24 Kbytes...
Page 22 CHAPTER 1 OVERVIEW Table 1.1-1 MB90330 Series Product Lineup List (2/2) Product name MB90V330A * MB90F334A MB90333A MB90334A DTP/external interrupt Input count: 8 Interrupt factor: rising edge/falling edge/"L" level/"H" level selectable USB Function (Conforming to USB2.0 Full Speed) Supports Full speed Endpoint are specifiable up to six.
Page 23: Block Diagram
CHAPTER 1 OVERVIEW Block Diagram Figure 1.2-1 shows the block diagram of a MB90330 series. Block Diagram of the MB90330 Series Figure 1.2-1 Block Diagram of the MB90330 Series X0,X1 Clock X0A,X1A control circuit MC-16LX core Port 6 RAM(28Kbyte)* P67/INT7/SDA0 External interrupt P66/INT6/SCL0 (ch0 to 7)
Page 24: Package Dimension
(Mounting height) +.008 .059 INDEX –.004 "A" ˚ LEAD No. 0.10±0.10 0.16±0.03 0.145±0.055 0.50±0.20 (.004±.004) 0.40(.016) 0.07(.003) (.006±.001) (.006±.002) (.020±.008) (Stand off) 0.60±0.15 0.25(.010) (.024±.006) Dimensions in mm (inches). 2003 FUJITSU LIMITED F120006S-c-4-5 Note: The values in parentheses are reference values.
Page 25 –.004 INDEX 0~8 ˚ "A" 0.10±0.05 LEAD No. (.004±.002) +0.05 (Stand off) 0.60±0.15 0.22±0.05 0.145 –0.03 0.50(.020) 0.08(.003) (.024±.006) (.009±.002) +.002 .006 –.001 0.25(.010) Dimensions in mm (inches). 2002 FUJITSU LIMITED F120033S-c-4-4 Note: The values in parentheses are reference values.
Page 26: Pin Assignment
CHAPTER 1 OVERVIEW Pin Assignment Figure 1.4-1 shows the pin assignments of a MB90330 series. Pin Assignment (LQFP-120) Figure 1.4-1 Pin Assignments of the MB90330 Series (LQFP-120) P30/A00/TIN1 P31/A01/TOT1 P32/A02/TIN2 P33/A03/TOT2 P34/A04 P55/HAK P35/A05 P54/HRQ P36/A06 P53/WRH P37/A07 P52/WRL P40/A08/TIN0 P51/RD P41/A09/TOT0 P50/ALE...
Page 27: Pin Function
CHAPTER 1 OVERVIEW Pin Function Table 1.5-1 describes the MB90330 series pin functions. Pin Function Table 1.5-1 Pin Function (1/7) Pin No. Pin Name Circuit Functional description Type It is oscillation terminal. It is oscillation terminal. It is 32 kHz oscillation terminal. It is 32 kHz oscillation terminal.
Page 28 CHAPTER 1 OVERVIEW Table 1.5-1 Pin Function (2/7) Pin No. Pin Name Circuit Functional description Type 113 to 116 P20 to P23 It is General-purpose input/output port. Functions as the general-purpose input/output port in the external bus mode if the bit corresponding to external address output control register (HACR) is set to "1".
Page 29 CHAPTER 1 OVERVIEW Table 1.5-1 Pin Function (3/7) Pin No. Pin Name Circuit Functional description Type It is General-purpose I/O port. Functions as the external address pin in non-multi-bus mode. TIN0 Functions as an event input pin for 16-bit reload timer ch0. It is General-purpose I/O port.
Page 30 CHAPTER 1 OVERVIEW Table 1.5-1 Pin Function (4/7) Pin No. Pin Name Circuit Functional description Type It is General-purpose I/O port. Functions as the data write strobe output (WRLX) pin on the lower side in external bus mode. Functions as a general-purpose I/O port when the WRE bit in the EPCR register is "0".
Page 31 CHAPTER 1 OVERVIEW Table 1.5-1 Pin Function (5/7) Pin No. Pin Name Circuit Functional description Type It is General-purpose I/O port (Withstand voltage of 5 V). INT5 Function as input pins for external interrupt ch5. Functions as the PWC input pin. It is General-purpose I/O port (Withstand voltage of 5 V).
Page 32 CHAPTER 1 OVERVIEW Table 1.5-1 Pin Function (6/7) Pin No. Pin Name Circuit Functional description Type 56 to 59 PA0 to PA3 It is General-purpose I/O port (Withstand voltage of 5 V). IN0 to IN3 Captures as trigger input for ch0 to ch3 of the input capture. 60 to 63 PA4 to PA7 It is General-purpose I/O port (Withstand voltage of 5 V).
Page 33 CHAPTER 1 OVERVIEW Table 1.5-1 Pin Function (7/7) Pin No. Pin Name Circuit Functional description Type It is power supply pin. It is power supply pin. It is power supply pin. It is power supply pin. It is power supply pin (GND). It is power supply pin (GND).
Page 34: I/O Circuit Types
CHAPTER 1 OVERVIEW I/O Circuit Types Table 1.6-1 shows I/O circuit types for pins of a MB90330 series. I/O Circuit Types Table 1.6-1 I/O Circuit Types (1/3) Classification Circuit Remarks • Oscillation return resistance: X1,X1A X1, X0about 1 MΩ X1A,X0A10 MΩ •...
Page 35 CHAPTER 1 OVERVIEW Table 1.6-1 I/O Circuit Types (2/3) Classification Circuit Remarks • CMOS hysteresis input with pull-up • Resistance: About 50 kΩ CMOS hysteresis input • CMOS output • CMOS hysteresis input Open drain control signal • With open drain control •...
Page 36 CHAPTER 1 OVERVIEW Table 1.6-1 I/O Circuit Types (3/3) Classification Circuit Remarks • USB I/O pins D + Input D - Input Differential input Full D + Output Full D - Output Low D + Output Low D - Output direction speed •...
Page 37: Handling Of Device
CHAPTER 1 OVERVIEW Handling of Device This section describes the precautions when handling devices. Precautions when Handling Devices Preventing Latch-up, Turning on Power Supply Latch-up may occur on CMOS IC under the following conditions: • If a voltage higher than V or lower than V is applied to input and output pins, •...
Page 38 CHAPTER 1 OVERVIEW About Crystal oscillator circuit Noise near the X0/X1 pins and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1 pins and X0A/X1A pins, the crystal oscillator (or the ceramic oscillator) and the bypass capacitor to ground are located as close to the device as possible.
Page 39 CHAPTER 1 OVERVIEW Caution on Operations during PLL Clock Mode Even if the oscillator comes off or the clock input stops with the PLL clock selected for this microcontroller, the microcontroller may continue to operate at the free-running frequency of the PLL internal automatic oscillator circuit.
Page 40 CHAPTER 1 OVERVIEW...
Page 41: Chapter 2 Cpu
CHAPTER 2 This chapter describes specifications, memories and register functions to know the MB90330 series. 2.1 Outline Specification of CPU 2.2 Memory Space 2.3 Register of CPU 2.4 Prefix Code...
Page 42: Outline Specification Of Cpu
CHAPTER 2 CPU Outline Specification of CPU The outline specification of CPU is explained. Outline Specification of CPU The F MC-16LX CPU core is the 16-bit CPU designed for applications requiring the high-speed real-time process for house hold device, etc. The F MC-16LX instruction set is designed for controller applications enabling the high-speed and high-efficiency control process.
Page 43: Memory Space
CHAPTER 2 CPU Memory Space The F MC-16LX CPU has the 16 Mbytes memory space in which all inputs and outputs of data program that are administered by the F MC-16LX CPU are placed in this 16 Mbytes memory space. The CPU indicates these addresses with the 24-bit address bus and accesses each resource.
Page 44 CHAPTER 2 CPU Address Generation Type In F MC-16LX CPU, there is two address generation method. One is the linear addressing to specify the entire 24-bit address by the instruction and the other is the bank addressing to specify the upper 8-bit address and the lower 16-bit address by an appropriate bank register and the instruction, respectively.
Page 45 CHAPTER 2 CPU Addressing Types by Bank The bank addressing specifies the bank for each space by five bank registers as shown below by dividing the 16 Mbytes space into 256 of 64 Kbytes banks: Program bank register (PCB) Data bank register (DTB) User stack bank register (USB) System stack bank register (SSB) Additional data bank register (ADB)
Page 46 CHAPTER 2 CPU Figure 2.2-4 Physical address of Each Space FFFFFF Program space FF0000 PCB (Program bank register) B3FFFF Additional space ADB (Additional data bank register) B30000 92FFFF User stack space 920000 USB (User stack bank register) 68FFFF Data space DTB (Data bank register) 680000 4BFFFF...
Page 47 CHAPTER 2 CPU Multi Byte Length Data Access Fundamentally, accesses are made within a bank. For an instruction accessing a multi-byte data item, address FFFF is followed by address 0000 of the same bank. Figure 2.2-6 is an example of an instruction accessing multi-byte data.
Page 48: Register Of Cpu
CHAPTER 2 CPU Register of CPU The F MC-16LX registers can be roughly grouped into two types, the special registers in the CPU and the general-purpose registers in memory. Special registers are a dedicated hardware for the CPU inside, and their use is limited by the CPU architecture. General- purpose registers share the CPU address space with the RAM.
Page 49 CHAPTER 2 CPU General-purpose Register Figure 2.3-1 Configuration of Dedicated Registers Accumulator User stack pointer System stack pointer Processor status Program counter Direct page register Program bank register Data bank register User stack bank register System stack bank register Additional data bank register 8 bit 16 bit 32 bit...
Page 50: Accumulator (A)
CHAPTER 2 CPU 2.3.1 Accumulator (A) The function of accumulator (A) is explained. Accumulator (A) The accumulator (A) consists of two 16-bit length arithmetic operation registers (AH/AL) to be used for the temporary storage of operation result and data transfer, etc. The AH and the AL are concatenated to be used for the 32 bit data process.
Page 51: User Stack Pointer (Usp) And System Stack Pointer (Ssp)
CHAPTER 2 CPU 2.3.2 User Stack Pointer (USP) and System Stack Pointer (SSP) Functions of the user stack pointer (USP) and the system stack pointer (SSP) are described here. User Stack Pointer (USP) and System Stack Pointer (SSP) The user stack pointer (USP) and the system stack pointer (SSP) are 16-bit registers indicating the memory addresses for data saving or restoring at execution of a push or pop instruction or a subroutine.
Page 52: Processor Status (Ps)
CHAPTER 2 CPU 2.3.3 Processor Status (PS) The function of processor status (PS) is explained. Processor Status (PS) The processor status (PS) consists of bits to perform the CPU operation and to indicate the CPU status. As shown in Figure 2.2-6, the upper byte of PS register consists of the register bank pointer (RP) and the interrupt level mask register (ILM).
Page 53 CHAPTER 2 CPU Zero flag (Z) If the operation result is all 0, Z flag is set, and, besides, cleared. Overflow flag (V) The V flag is set and cleared when a signed numeric value overflow occurs and does not occur, respectively, as a result of operation execution.
Page 54 CHAPTER 2 CPU Table 2.3-1 Level Indicated by Interrupt Level Mask Register (ILM) ILM2 ILM1 ILM0 Level value Acceptable interrupt level Disables the interrupt. Only 0 Small level value smaller than 1 Small level value smaller than 2 Small level value smaller than 3 Small level value smaller than 4 Small level value smaller than 5 Small level value smaller than 6...
Page 55: Program Counter (Pc)
CHAPTER 2 CPU 2.3.4 Program Counter (PC) The function of program counter (PC) is explained. Program Counter (PC) The PC is a 16-bit counter to indicate the lower 16 bits of memory address of the instruction code to be executed by the CPU. The upper 8-bit address is indicated by the program bank register (PCB). The PC content is updated by the conditional branch instruction, the subroutine call instruction, the interrupt, the reset, etc.
Page 56: Program Bank Register (Pcb)
CHAPTER 2 CPU 2.3.5 Program Bank Register (PCB) The function of program bank register (PCB) is explained. Program Bank Register (PCB) <Initial Value: Value in Reset Vector> Program bank register (PCB) consists of the following registers: • Data bank register (DTB) <Initial value:00 >...
Page 57: Direct Page Register (Dpr)
CHAPTER 2 CPU 2.3.6 Direct Page Register (DPR) The function of direct page register (DPR) is explained. Direct Page Register (DPR) <Initial Value:01 > The direct page register (DPR) specifies the addresses 8 to addresses 15 of instruction operand in the direct addressing mode as shown in Figure 2.3-11.
Page 58: General-Purpose Registers (Register Bank)
CHAPTER 2 CPU 2.3.7 General-purpose Registers (Register Bank) Functions of general-purpose registers (register bank) are described here. General-purpose Registers (Register Bank) The register bank consisting of 8 words can be used as the general-purpose register for arithmetic operations of the byte register (R0 to R7), the word register (RW0 to RW7), and the long word register (RL0 to RL3).
Page 59: Prefix Code
CHAPTER 2 CPU Prefix Code A part of instruction operation can be changed by placing the prefix code before the instruction. Three types of prefix codes can be used: • The bank select prefix • The common register bank prefix •...
Page 60 CHAPTER 2 CPU POPW PS The SSB or the USB is used according to the S flag regardless of the prefix. The effect of the prefix reaches the following instruction. MOV ILM,#imm8 The instruction operation is normal although the prefix continuously affects the next instruction. RETI SSB is used regardless of the prefix.
Page 61 CHAPTER 2 CPU Interrupt instruction (INT #vct8,INT9,INT addr16,INTO addr24,POPW PS) The CCR is changed as specified by the instruction regardless of the prefix. JCTX@A The CCR is changed as specified by the instruction regardless of the prefix. MOV ILM,#imm8 The instruction operation is normal although the prefix continuously affects the next instruction.
Page 62 CHAPTER 2 CPU Interrupt Suppression Instruction The interrupt request is not sampled for the following 10 types of instructions: MOV ILM,#imm8/PCB/SPB/OR CCR,#imm8/NCC AND CCR,#imm8/ADB/CMR/POPW PS/DTB When a valid interrupt request occurs during the execution of one of the above instructions, the interrupt can be processed only if an instruction other than the above is executed.
Page 63: Chapter 3 Interrupt
CHAPTER 3 INTERRUPT This chapter describes the interruption, extended intelligent I/O service (EI OS), and direct memory access controller (µDMAC) of MB90330 Series. 3.1 Outline of Interrupt 3.2 Interrupt Cause and Interrupt Vector 3.3 Interrupt Control Register and Peripheral Function 3.4 Hardware Interrupt 3.5 Software Interrupt 3.6 Interrupts by Extended Intelligent I/O Service (EI...
Page 64: Outline Of Interrupt
CHAPTER 3 INTERRUPT Outline of Interrupt MC-16LX has the following five interrupt functions, which suspend the current process when an event occurs and transfer control to a separately defined program. • Hardware Interrupt • Software interrupt • Interrupts by extended intelligent I/O service (EI µ...
Page 65 CHAPTER 3 INTERRUPT Software interrupt Transfers control to the user-defined interrupt handing program by executing the instruction dedicated to software interrupt (for example, INT instruction). Figure 3.1-2 Overview of Software Interrupts Register file : Processor status : Interrupt enable flag B unit : Interrupt level mask register Microcode...
Page 66 CHAPTER 3 INTERRUPT Interruption by µDMAC µDMAC is involved in automatic data transfer between peripheral functions and memory. EI OS performs data transfer by DMA transfer although it was previously performed by the interrupt handling program. Once the data transfer process has been performed the specified number of times, µDMAC automatically executes the interrupt handling program.
Page 67: Interrupt Cause And Interrupt Vector
CHAPTER 3 INTERRUPT Interrupt Cause and Interrupt Vector MC-16LX has functions that are associated with 256 types of interrupt causes, and 256 interrupt vector tables are assigned to the most significant address area of memory. This interruption vector is shared by all the interruptions. All of interrupt INT0 to INT255 are available for software interrupt, although some interrupt vectors are shared with hardware interrupt or exception processing interrupt.
Page 68 CHAPTER 3 INTERRUPT Interrupt Factors, Interrupt Vectors, and Interrupt Control Registers Table 3.2-2 shows the relationship between the causes of interrupts except software interrupt, and the interrupt vectors and control registers. Table 3.2-2 Interrupt Factors, Interrupt Vectors, and Interrupt Control Registers Interrupt control Interrupt vector µDMAC-...
Page 69 CHAPTER 3 INTERRUPT : Available. With EI OS stop function. (The interrupt request flag is cleared by the interrupt clear signal. With a stop request.) : Available. (The interrupt request flag is cleared by the interrupt clear signal.) ∆ : Available when not using the interrupt factor shared with ICR : Not available *1: The interrupt levels for the peripheral functions sharing the ICRs are identical.
Page 70: Interrupt Control Register And Peripheral Function
CHAPTER 3 INTERRUPT Interrupt Control Register and Peripheral Function Interrupt control registers (ICR00 to ICR15) located in the interrupt controller, are associated with all the peripheral functions which have the interrupt function. This register controls the interrupt and the extended intelligent I/O service (EI OS).
Page 71 CHAPTER 3 INTERRUPT Interrupt Control Register Functions Each of the interrupt control register (ICR) has the following four functions. • Setting of interrupt level for peripheral function • Selection of whether to perform normal interrupt or external intelligent for corresponding peripheral function (EI •...
Page 72: Interrupt Control Registers (Icr00 To Icr15)
CHAPTER 3 INTERRUPT 3.3.1 Interrupt Control Registers (ICR00 to ICR15) Interrupt control registers (ICR00 to ICR15) associated with all the peripheral functions provided with the interrupt function, controls the handling which takes place when an interrupt request is generated. Some functions of the registers are different between write and read.
Page 73 CHAPTER 3 INTERRUPT Figure 3.3-2 Interrupt Control Register (ICR00 to ICR15) at Read At read Address Initial value 0000B0 - - 000111 0000BF Interrupt level set bit Interrupt level 0 (Highest) Interrupt level 7 (No interrupt) OS enable bit Activate interrupt sequence during generation of an interrupt. Activate EI OS during generation of an interrupt.
Page 74: Interrupt Control Register Functions
CHAPTER 3 INTERRUPT 3.3.2 Interrupt Control Register Functions Each of the interrupt control register (ICR00 to ICR15) consists of the following bits, which have four functions. • Interrupt level set bit (IL2 to IL0) • EI OS enable bit (ISE) •...
Page 75 CHAPTER 3 INTERRUPT Interrupt Control Register Functions Interrupt level set bit (IL2 to IL0) Specifies the interrupt level for the associated peripheral function. Initialized to level 7 (no interrupts) by reset. Table 3.3-2 shows the relationship between the interrupt level set bits and each interrupt level. Table 3.3-2 Correspondence between Interrupt Level Set Bits and Interrupt Levels Interrupt level 0 (highest interrupt)
Page 76 CHAPTER 3 INTERRUPT Table 3.3-3 Correspondence between EI OS Channel Select Bits and Descriptor Addresses ICS3 ICS2 ICS1 ICS0 Channel to be selected Descriptor address 000100 000108 000110 000118 000120 000128 000130 000138 000140 000148 000150 000158 000160 000168 000170 000178 OS status bits (S1 and S0) It is a bit only for reading.
Page 77: Hardware Interrupt
CHAPTER 3 INTERRUPT Hardware Interrupt Hardware interrupt suspends the active program execution by the CPU in response to an interrupt request signal generated by a peripheral function, resulting in transfer of control to the user-defined interrupt handling program. Extended intelligent I/O service OS), µDMAC, external interrupts, and other similar processes are also executed as a type of hardware interrupt.
Page 78 CHAPTER 3 INTERRUPT Construction of Hardware Interrupt As shown in Table 3.4-1, there are four features related to hardware interrupt. These four must be programmed when hardware interrupt is used. Table 3.4-1 Mechanism Related to Hardware Interrupt Mechanism related to hardware Functions interrupt Interrupt enable bits, interrupt request...
Page 79 CHAPTER 3 INTERRUPT Hardware interrupt suppression of interrupt suppression instruction Table 3.4-2 shows the hardware interrupt suppression instruction. If the hardware interrupt request is generated during execution of hardware interrupt suppression instruction, an interrupt is processed after execution of hardware interrupt suppression instruction and then other instruction. Table 3.4-2 Hardware Interrupt Suppression Instruction Interruption/holding control instruction Prefix code...
Page 80: Operation Of Hardware Interrupt
CHAPTER 3 INTERRUPT 3.4.1 Operation of Hardware Interrupt The following describes the operation sequence from generation of a hardware interrupt request to completion of interrupt handling. Start of Hardware Interrupt Operation of peripheral function (generation of interrupt request) Any peripheral function provided with the hardware interrupt request function has "interrupt request flag" and "interrupt enable flag".
Page 81 CHAPTER 3 INTERRUPT Operation of Hardware Interrupt Figure 3.4-2 shows the operation sequence from generation of a hardware interrupt to completion of interrupt handling. Figure 3.4-2 Operation of Hardware Interrupt Internal bus PS, PC Microcode Check Comparator MC-16LX CPU Other peripheral function Peripheral function generated Interrupt request...
Page 82: Operation Flow Of Hardware Interrupt
CHAPTER 3 INTERRUPT 3.4.2 Operation Flow of Hardware Interrupt When the peripheral function generates an interrupt request, the interrupt controller notifies the CPU of the interrupt level. If the CPU is ready to accept the interrupt, it suspends the currently active instruction; the CPU then executes the interrupt handling OS) µDMAC.
Page 83: Procedure For Using A Hardware Interrupt
CHAPTER 3 INTERRUPT 3.4.3 Procedure for Using a Hardware Interrupt Use of hardware interrupt requires the system stack area, peripheral functions, and interrupt control registers (ICR) to be set up. Procedure for Using a Hardware Interrupt Figure 3.4-4 shows an example of the procedure for using a hardware interrupt. Figure 3.4-4 Example of Procedure for Using a Hardware Interrupt START Setting System stack area...
Page 84: Multiple Interrupts
CHAPTER 3 INTERRUPT 3.4.4 Multiple Interrupts Multiple hardware interrupts can be implemented. To do so, set different interrupt levels for interrupt level set bits (IL0 to IL2) of the ICR in response to two or more interrupt OS and multiple µDMAC requests from a peripheral function.
Page 85 CHAPTER 3 INTERRUPT Example of Multiple Interrupts Aa an example of multiple interrupt processing, set the A/D converter interrupt level to 2 and the timer interrupt level to "1", considering a case when timer interrupts are to be given higher priority than A/D converter interrupts.
Page 86: Hardware Interrupt Processing Time
CHAPTER 3 INTERRUPT 3.4.5 Hardware Interrupt Processing Time Before the interrupt handling routine can be executed after a hardware interrupt request is generated, the time to complete of the currently active instruction and the interrupt handling time are required. Hardware Interrupt Processing Time Before the interrupt handling routine can be executed after an interrupt request is generated and the interrupt is accepted, the waiting time for the interrupt request sample and the interrupt handling time (required for preparation for interrupt handling) are required.
Page 87 CHAPTER 3 INTERRUPT Interrupt handling time (θ machine cycle) The CPU must save the dedicated registers in the system stack, fetch the interrupt vectors, and execute other processes by acceptance of the interrupt request. To do so, it requires the interrupt handling time with the θ...
Page 88: Software Interrupt
CHAPTER 3 INTERRUPT Software Interrupt The software interrupt function transfers control from the currently active program by the CPU to the user-defined interrupt handling program in response to execution of the software interrupt instruction (INT instruction). The hardware interrupt stops during execution of a software interrupt. Start of Software Interrupt Start of software interrupt A software interrupt is started by using the INT instruction.
Page 89 CHAPTER 3 INTERRUPT Operation of Software Interrupt Figure 3.5-1 shows the operation sequence from generation of a software interrupt to completion of interrupt handling. Figure 3.5-1 Operation of Software Interrupt Internal bus PS, PC (2) Microcode Queue Fetch PS : Processor status : Interrupt enable flag S : Stack flag IR : Instruction register...
Page 90: Interrupts By Extended Intelligent I/O Service (Ei 2 Os)
CHAPTER 3 INTERRUPT Interrupts by Extended Intelligent I/O Service (EI The extended intelligent I/O service (EI OS) executes automatic data transfer between the peripheral function (I/O) and memory. A hardware interrupt is generated at the end of the data transfer. Extended Intelligent I/O Service (EI The extended intelligent I/O service is a kind of hardware interrupts.
Page 91 CHAPTER 3 INTERRUPT Operation of Extended Intelligent I/O Service (EI Figure 3.6-1 shows the operation of the EI Figure 3.6-1 Operation of Extended Intelligent I/O Service (EI Memory space Peripheral by IOA function (I/O) I/O register I/O register Interrupt request by ICS Interrupt control register (ICR) Interrupt controller...
Page 92: Extended Intelligent I/O Service
CHAPTER 3 INTERRUPT 3.6.1 Extended Intelligent I/O Service (EI OS) Descriptor (ISD) Extended intelligent I/O service (EI OS) descriptor (ISD) is existed to the addresses " in the internal RAM and consists of 8 bytes × 16 channels. "000100 " to "00017F Configuration of Extended Intelligent I/O Service (EI OS) Descriptor (ISD) Configuration of ISD consists of 8 bytes ×...
Page 93 CHAPTER 3 INTERRUPT Table 3.6-1 Correspondence between Channel Numbers and Descriptor Addresses Channel Descriptor address 000100 000108 000110 000118 000120 000128 000130 000138 000140 000148 000150 000158 000160 000168 000170 000178...
Page 94: Each Register Of Extended Intelligent I/O Service
CHAPTER 3 INTERRUPT 3.6.2 Each Register of Extended Intelligent I/O Service (EI Descriptor (ISD) The extended intelligent I/O service (EI OS) descriptor (ISD) consists of the following registers. • Data counter (DCT) • I/O register address pointer (IOA) • EI OS status register (ISCS) •...
Page 95 CHAPTER 3 INTERRUPT Extended Intelligent I/O Service (EI OS) Status Register (ISCS) The extended intelligent I/O service status register (ISCS) updates or fixes the buffer address and I/O register address pointers by the 8-bit length register. It also indicates the transfer data format (byte or word) and the direction of transfer.
Page 96 CHAPTER 3 INTERRUPT Buffer address Pointer (BAP) The buffer address pointer (BAP), a 24-bit register, contains the address used for the next attempt of transfer by EI OS. The BAP is provided independently for the EI OS channels to enable the EI channels to transfer data between any address of 16 Mbytes and I/O.
Page 97: Operation Of Extended Intelligent I/O Service (Ei 2 Os)
CHAPTER 3 INTERRUPT 3.6.3 Operation of Extended Intelligent I/O Service (EI If the peripheral function has generated an interrupt request and activation of EI OS has been set in the associated interrupt control register (ICR), the CPU will execute data transfer using EI OS.
Page 98: Procedure For Use Of Extended Intelligent I/O Service (Ei 2 Os)
CHAPTER 3 INTERRUPT 3.6.4 Procedure for use of Extended Intelligent I/O Service (EI To use extended intelligent I/O service (EI OS), the system stack area, EI OS descriptor, peripheral function, interrupt control register (ICR), and other requirements must be set Procedure for Use of Extended Intelligent I/O Service (EI Figure 3.6-8 shows the EI OS software and the process by hardware.
Page 99: Os) Processing Time
CHAPTER 3 INTERRUPT 3.6.5 Extended Intelligent I/O Service (EI OS) Processing Time The time required for extended intelligent I/O service (EI OS) processing depends on the following factors: • Setting of EI OS status register (ISCS) • Address (area) indicating I/O register address pointer (IOA) •...
Page 100 CHAPTER 3 INTERRUPT Further, correction may be required, depending on the condition for executing EI OS, as shown in Table 3.6-3. Table 3.6-3 Compensation Value for Data Transfer at EI OS Processing Time I/O register address pointer Internal Access External access B/Even B/Even 8/Odd...
Page 101 CHAPTER 3 INTERRUPT At the end caused by an end request from the peripheral function (I/O) If data transfer by EI OS is aborted due to an end request from the peripheral function (I/O) (ICR S1, ICR S0 = 11), the hardware interrupt is activated without performing data transfer. The EI OS processing time is calculated using the expression below.
Page 102: Exception Processing Interrupt
CHAPTER 3 INTERRUPT Exception Processing Interrupt MC-16LX executes exception handling by executing undefined instructions. Exception handling, basically the same as interrupt, is executed when an exception item is detected during a period between instructions, the normal process is suspended for this purpose.
Page 103: Interruption By Μdmac
CHAPTER 3 INTERRUPT Interruption by µDMAC µDMAC is a simplified DMA with the same function as EI 3.8.1 µDMAC Function 3.8.2 Register of µDMAC 3.8.2.1 DMA Descriptor Channel Specification Register (DCSR) 3.8.2.2 DMA Status Register (DSRH/DSRL) 3.8.2.3 DMA Stop Status Register (DSSR) 3.8.2.4 DMA Permission Register (DERH/DERL) 3.8.3 DMA Descriptor Window Register (DDWR) 3.8.3.1 DMA Data Counter (DDCTH/DDCTL)
Page 104: Μdmac Function
CHAPTER 3 INTERRUPT µDMAC Function 3.8.1 µDMAC is simple DMA with the function equal with EI µDMAC Function µDMAC has the following functions. • Performs automatic data transfer between the peripheral resource (I/O) and memory. • The program execution of CPU stops in the DMA startup. •...
Page 105: Register Of Μdmac
CHAPTER 3 INTERRUPT Register of µDMAC 3.8.2 µDMAC has four registers: DCSR, DSR, DSSR, and DER. The DMA descriptor used to set up DMA transfer is described in "3.8.3 DMA Descriptor Window Register (DDWR)". µDMAC Register List Figure 3.8-1 µDMA Register List DMA descriptor channel specification register (DCSR) DCSR 00009B...
Page 106: Dma Descriptor Channel Specification Register (Dcsr)
CHAPTER 3 INTERRUPT 3.8.2.1 DMA Descriptor Channel Specification Register (DCSR) DMA descriptor channel specification register (DCSR) switches the descriptor of each channel. The descriptor is set after the channel is specified by this register. DMA Descriptor Channel Specification Register (DCSR) Figure 3.8-2 DMA Descriptor Channel Specification Register DCSR 00009B...
Page 107 CHAPTER 3 INTERRUPT One descriptor channel of the 16 channels is selected by setting the DCSR. For details, see "3.8.3 DMA Descriptor Window Register (DDWR) " *: This function can use even when Mini-HOST is operated. [bit15] STP:STP control bit STP bit Function 0 [Initial value]...
Page 108: Dma Status Register (Dsrh/Dsrl)
CHAPTER 3 INTERRUPT 3.8.2.2 DMA Status Register (DSRH/DSRL) DMA status register (DSRH/DSRL) indicates that the DMA transfer ended. When "1" is set to this register, the interrupt is generated at the same time. Bit Configuration of DMA Status Register (DSRH/DSRL) Figure 3.8-3 Bit Configuration of DMA Status Register (DSRH/DSRL) 00009D DTE15 DTE14 DTE13 DTE12 DTE11 DTE10 DTE9...
Page 109: Dma Stop Status Register (Dssr)
CHAPTER 3 INTERRUPT 3.8.2.3 DMA Stop Status Register (DSSR) DMA stop status register (DSSR) indicates that the DMA transfer stopped due to the STOP request. The meaning of the bit in this register is different depending on the STP bit of the DMA descriptor channel specification register (DCSR).
Page 110: Dma Permission Register (Derh/Derl)
CHAPTER 3 INTERRUPT 3.8.2.4 DMA Permission Register (DERH/DERL) DMA permission register (DERH/DERL) enables the DMA transfer. When "1" is set to this register, the interrupt request, which is the DMA transfer request, generates to the corresponding channel, and starts the DMA transfer. DMA Permission Register (DERH/DERL) Figure 3.8-5 Bit Configuration of DMA Permission Register (DERH/DERL) DERH...
Page 111: Dma Descriptor Window Register (Ddwr)
CHAPTER 3 INTERRUPT 3.8.3 DMA Descriptor Window Register (DDWR) The DMA descriptor, consisting of 8 bytes × 16 channels, is used to set up DMA transfer. One of the 16 channels is specified, and mapped to the DMA descriptor window register (DDWR) for being accessible.
Page 112: Dma Data Counter (Ddcth/Ddctl)
CHAPTER 3 INTERRUPT 3.8.3.1 DMA Data Counter (DDCTH/DDCTL) DMA data counter (DDCTH/DDCTL) sets the data transfer. When DDCTH/DDCTL is 0, the DMA transfer ends. DMA Data Counter (DDCTH/DDCTL) DMA data counter (DDCTH/DDCTL), a 16-bit length register, indicates the counter associated with transferred number.
Page 113: Dma I/O Register Address Pointer (Dioah/Dioal)
CHAPTER 3 INTERRUPT 3.8.3.2 DMA I/O Register Address Pointer (DIOAH/DIOAL) DMA I/O register address pointer (DIOAH/DIOAL) sets the I/O address pointer. The upper address (A23 to A16) is fixed at "00 ". DMA I/O Register Address Pointer (DIOAH/DIOAL) The DMA I/O register address pointer (DIOAH/DIOAL), a 16-bit length register, indicates the 16 low order bits (A15 to A00) of the DMA I/O register address.
Page 114: Dma Control Register (Dmacs)
CHAPTER 3 INTERRUPT 3.8.3.3 DMA Control Register (DMACS) DMA control register (DMACS) controls the DMA transfer. The following can be controlled by the DMACS. → → • Direction control (IOA BAP and BAP IOA) • Transfer bit length (Byte and word) •...
Page 115 CHAPTER 3 INTERRUPT Figure 3.8-10 Wait Specification Bit Explanation source destination wait source destination Length of wait part in transfer such as above figure is defined by RDY2 and RDY1. Note: If writing transmission data to UART by using µDMAC, not setting RDY2 and RDY1 bit of DMACS register in (0, 0).
Page 116: Dma Buffer Address Pointer (Dbaph/Dbapm/Dbapl)
CHAPTER 3 INTERRUPT 3.8.3.4 DMA Buffer Address Pointer (DBAPH/DBAPM/DBAPL) DMA buffer address pointer (DBAPH/DBAPM/DBAPL) sets the buffer address pointer. The DBAPH/DBAPM/DBAPL can be set A23 to A00. DMA Buffer Address Pointer (DBAPH/DBAPM/DBAPL) The DMA buffer address pointer (DBAPH/DBAPM/DBAPL), a 24-bit register, contains the address used for DMA transfer.
Page 117: Explanation Of Operation Of Μdmac
CHAPTER 3 INTERRUPT Explanation of Operation of µDMAC 3.8.4 This section describes the µDMAC operation. Operation of µDMAC Figure 3.8-12 shows the DBAP operation. Data transfer using µDMAC performs the following steps in order: 1. The peripheral resource (I/O) makes a request for DMA transfer. 2.
Page 118 CHAPTER 3 INTERRUPT µDMAC Use Procedure Figure 3.8-13 shows the procedure for using µDMAC. Figure 3.8-13 Use Procedure of µDMAC Software processing Hardware processing (Interrput generation) START ENx=1 of appropreate ch Setting System stack area STOP request Initializing peripheral function and SE=1 DMA transfer Setting Interrupt control register...
Page 119: Exceptions
Exception processing is fundamentally the same as interrupt processing. When an exception is detected between instructions, exception processing is performed separately from ordinary processing. In general, exception processing is performed as a result of an unexpected operation. Fujitsu recommends using exception processing only for debugging or for activating emergency recovery software.
Page 120: Stack Operation Of Interrupt Processing
CHAPTER 3 INTERRUPT 3.10 Stack Operation of Interrupt Processing Once an interrupt is accepted, the contents of the dedicated registers are automatically saved in the system stack before control branches to the interrupt handling. Return from the stack at the end of the interrupt handling also takes place automatically. Stack Operation at the Start of Interrupt Processing Once the interrupt is accepted, the CPU automatically saves the contents of the current dedicated registers and their related data in the system stack in the order below:...
Page 121 CHAPTER 3 INTERRUPT Stack Area Securing stack area The stack area is used to save or return the program counter (PC) used to execute the subroutine call (CALL) or vector call (CALLV) instruction as well as execute the interrupt handling. This area is also used, by the PUSHW or POPW instruction, to save or return the contents of temporary registers and their related data.
Page 122: Program Example Of Interrupt Processing
CHAPTER 3 INTERRUPT 3.11 Program Example of Interrupt Processing An example of interrupt processing program is shown below. Program Example of Interrupt Processing Processing specification An example interruption program that uses external interruption 0 (INT0) Coding example DDR6 000016H ; Port 6 direction register ENIR 00003CH ;...
Page 123 CHAPTER 3 INTERRUPT LOOP ; Unconditional jump ;----------Interrupt Program------------------------------------------------------------ ED_INT1: I:EIRR, #00H ; New acceptance of INT0 prohibited RETI ; Returns from interrupt. CODE ENDS ;----------Vector Settings------------------------------------------------------------------ VECT CSEG ABS=0FFH 0FFB4H ; The vector is set in interruption #18(12H) ED_INT1 0FFDCH ;...
Page 124 CHAPTER 3 INTERRUPT Coding example DDR6 000016H ; Port 6 direction register ENIR 00003CH ; Interruption/DTP permission register EIRR 00003DH ; Interruption/DTP factor register ELVR 00003EH ; A register to specify the required level ICR03 0000B3H ; Interrupt control registers 03 BAPL 000100H ;...
Page 125 CHAPTER 3 INTERRUPT DCTL,#64H ; Sets transfer byte count (100 bytes) DCTH,#00H I:ICR00,#00001000B ; EI OS channel 0, EI OS enable, interrupt level 0 (highest) I:ELVR,#00000001B ; Make INT0 "H" level request I:EIRR,#00H ; Clears interrupt cause for INT0. I:ENIR,#01H ;...
Page 126: Delayed Interrupt Generation Module
CHAPTER 3 INTERRUPT 3.12 Delayed Interrupt Generation Module The delayed interrupt generation module is used to generate a task switching interrupt. Use of this module enables F MC-16LX CPU to generate or cancel an interrupt request. Block Diagram of Delayed Interrupt Generation Module Figure 3.12-1 shows the block diagram of the delayed interrupt generation module.
Page 127: Operation Of Delayed Interrupt Generation Module
CHAPTER 3 INTERRUPT 3.12.1 Operation of Delayed Interrupt Generation Module When the CPU writes "1" to the appropriate bit of the DIRR by software, the request latch in the delay interrupt generation module is set, resulting in generation of the interrupt request to the interrupt controller.
Page 128 CHAPTER 3 INTERRUPT...
Page 129: Chapter 4 Reset
CHAPTER 4 RESET This chapter explains reset of the MB90330 series. 4.1 Outline of Reset 4.2 Reset Factors and Oscillation Stabilization Wait Times 4.3 External Reset Pin 4.4 Reset Operation 4.5 Reset Factor Bit 4.6 State of Each Pin at Reset...
Page 130: Outline Of Reset
CHAPTER 4 RESET Outline of Reset When the reset cause is generated, the CPU suspends the currently executed process immediately before entering the wait state for release of the reset. After the reset is cleared, processing starts from the address indicated in the reset vector. There are the following four kinds of factors of resets.
Page 131 CHAPTER 4 RESET External reset An external reset is generated by inputting the "L" level signal to external reset pin (RST). The input time of the "L" level signal to the (RST) pin must be continued for 16 machine cycles (16/φ) or more. The external reset, that is, the RST pin input reset does not produce the oscillation stabilization wait time.
Page 132: Reset Factors And Oscillation Stabilization Wait Times
CHAPTER 4 RESET Reset Factors and Oscillation Stabilization Wait Times There are four kinds of reset factors of MB90330 series. The oscillation stabilization wait time varies with the reset cause. Reset Factors and Oscillation Stabilization Wait Times Table 4.2-1 shows the relationship between the reset causes and the oscillation stabilization wait time. Table 4.2-1 Reset Factors and Oscillation Stabilization Wait Times Reset factor Oscillation stabilization wait time...
Page 133 CHAPTER 4 RESET Figure 4.2-1 Oscillation Stabilization Wait Times for the Evaluation/flash and MASK Products during Power on Reset Time Evaluation/Flash Products /HCLK /HCLK operation Down-conversion Oscillation Stabilizing Stabilizing Wait Time Wait Time MASK Products /HCLK operation Oscillation Stabilizing Wait Time HCLK : Oscillation clock Note:...
Page 134: External Reset Pin
CHAPTER 4 RESET External Reset Pin The external reset pin (RST pin), dedicated to reset input pin, generates an internal reset in response to input of the "L" level signal. MB90330 series are reset in sync with the CPU operating clock, except for external pin in asynchronous (generated through ports and so on), which change to the reset state.
Page 135: Reset Operation
CHAPTER 4 RESET Reset Operation Once the reset is released, the object from which to read the mode data and reset vector is selected by setting the mode pin, before the mode fetch is performed. This fetch determines the CPU operation mode and the execution activation address succeeding the reset operation.
Page 136 CHAPTER 4 RESET Mode Fetch Once the reset is released, the CPU transfers the reset vector and mode data into the appropriate register in the CPU core. The reset vector and mode data are assigned to the four bytes of FFFFDC to FFFFDF When the reset is released, the CPU immediately outputs these addresses to the bus before fetching the reset vector and mode data.
Page 137: Reset Factor Bit
CHAPTER 4 RESET Reset Factor Bit A reset factor can be identified by reading the watchdog timer control register (WDTC). Reset Factor Bit There are the flip-flop registers associated with respective reset causes, as shown in Figure 4.5-1. The contents of the flip-flops are obtained by reading the watchdog timer control register (WDTC). If the reset cause needs to be identified after the reset has been released, the values read from the WDTC register should be processed by software before control branches to the program.
Page 138 CHAPTER 4 RESET Correspondence of Reset Factor Bit and Reset Factor Figure 4.5-2 shows the configuration of the reset cause bits of the watchdog timer control register (WDTC). Contents of reset cause bits and associated reset causes are shown in the Table 4.5-1. For details, see the "10.2 Watchdog Timer Control Register (WDTC)"...
Page 139: State Of Each Pin At Reset
CHAPTER 4 RESET State of Each Pin at Reset This section explains the state of each pin at reset. Pin Status during Reset The state of each pin during reset is determined by the settings of the mode pins (MD2 to MD0). When internal vector mode has been set: (MD2 to MD0="011 ") All I/O, or resource, pins are placed at high impedance.
Page 140 CHAPTER 4 RESET...
Page 141: Chapter 5 Clock
CHAPTER 5 CLOCK This chapter explains the clock of the MB90330 series. 5.1 Outline of Clock 5.2 Block Diagram of Clock Generation Section 5.3 Clock Select Register (CKSCR) 5.4 Clock Mode 5.5 Oscillation Stabilization Wait Time 5.6 Connection of Oscillator and External Clock...
Page 142: Outline Of Clock
CHAPTER 5 CLOCK Outline of Clock The clock generation section controls operation of the internal clock which is the operation clock for the CPU and peripheral functions. The following are four kinds of the clock. • Machine clock: Internal clock. •...
Page 143 CHAPTER 5 CLOCK Notes: • As for the oscillation clock, 1 MHz to 7 MHz can oscillate. The maximum operating frequency is 24 MHz for the CPU and peripheral functions. When multiplier exceeding the maximum operating frequency is specified, the device does not operate correctly. If the source oscillation at a frequency of 6 MHz, only 4-time frequency multiplication can be specified.
Page 144 CHAPTER 5 CLOCK Figure 5.1-1 Clock Supply Map Peripheral function Watchdog timer 16 - bit PPG timer PPG0 to PPG5 Clock generation unit 0/1/2/3/4/5 Watch timer 16 - bit PWC timer Timebase timer Subclock generation 8 - bit circuit expanded serial I/O PLL frequency multiplication circuit PCLK...
Page 145: Block Diagram Of Clock Generation Section
CHAPTER 5 CLOCK Block Diagram of Clock Generation Section The clock generation section consists of the following six blocks: • System clock generation circuit • Sub clock generation circuit • PLL multiplying circuit • Clock selector • Clock select register (CKSCR) •...
Page 146 CHAPTER 5 CLOCK Figure 5.2-1 Block Diagram of Clock Generation Section Low power consumption mode control register (LPMCR) CG1 CG0 Reserved Pin high Pin Hi-Z impedance control control circuit Internal reset Internal reset generation circuit CPU intermittent Intermittent cycle operation sector selection CPU clock CPU clock...
Page 147 CHAPTER 5 CLOCK PLL multiplying circuit The oscillation clock is multiplied by PLL oscillation and supplied to the CPU clock selector. Clock selector From the main and sub clocks, and the three PLL clocks, this selects the clock to be supplied to the CPU and periphery clock control circuits.
Page 148: Clock Select Register (Ckscr)
CHAPTER 5 CLOCK Clock Select Register (CKSCR) The clock select register (CKSCR) switches the clock mode between the main, sub, and PLL clocks, and selects the oscillation stabilization wait time and the PLL clock frequency multiplier. Configuration of Clock Select Register (CKSCR) Figure 5.3-1 shows the clock selection register (CKSCR) configuration.
Page 149 CHAPTER 5 CLOCK Note: The machine clock selection bit (MCS) is initialized by reset to main clock selection. Table 5.3-1 Functions of Clock Select Register (CKSCR) Bits (1/2) Bit name Functions • Bit indicating the main clock or sub clock, whichever selected as the machine clock. SCM: •...
Page 150 CHAPTER 5 CLOCK Table 5.3-1 Functions of Clock Select Register (CKSCR) Bits (2/2) Bit name Functions • Bit for selecting the multiply factor for PLL clock. • The multiplier can be selected from among three options. CS1, CS0: • Initialized to "00 "...
Page 151: Clock Mode
CHAPTER 5 CLOCK Clock Mode The clock modes are the main clock mode, PLL clock mode and sub clock mode. Main Clock Mode, PLL Clock Mode, Sub Clock Mode Main clock mode The main clock mode stops the PLL clock by using an oscillation clock frequency divided by 2 as the operating clock of the CPU and peripheral resources.
Page 152 CHAPTER 5 CLOCK Transition from PLL clock mode to sub clock mode If the sub clock selection bit (SCS) of the clock selection register (CKSCR) is rewritten from "1" to "0" while in the PLL clock mode, the mode changes from PLL clock to sub clock. Transition from sub clock mode to PLL clock mode If the SCS bit of the CKSCR is rewritten from "0"...
Page 153 CHAPTER 5 CLOCK Figure 5.4-1 State Transition Diagram of Machine Clock Selection Main MCS=1 MCM=1 SCS= 0 SCM=1 Main CS1, CS0= xx MCS=1 MCS=1 MCM=1 MCM=1 Main (14) SCS=1 SCS= 0 MCS=1 SCM=1 SCM= 0 MCM=1 (10) CS1, CS0= xx SCS=1 CS1, CS0= xx SCM=1...
Page 154: Oscillation Stabilization Wait Time
CHAPTER 5 CLOCK Oscillation Stabilization Wait Time When power is turned on, the stop mode is quit, or the clock mode changes from the sub to main or PLL clock, the oscillation stabilization wait time is required after the oscillation begins. This is because the oscillation of the oscillation clock remains in stopped state.
Page 155: Connection Of Oscillator And External Clock
CHAPTER 5 CLOCK Connection of Oscillator and External Clock MB90330 series, containing a system clock generator circuit, generates the clock with the oscillator connected externally. It is also possible to input an externally generated clock. Connection of Oscillator and External Clock Example of connection of crystal oscillator or ceramic oscillator Connect the crystal or ceramic oscillator as shown in Figure 5.6-1.
Page 156 CHAPTER 5 CLOCK...
Page 157: Chapter 6 Low-Power Consumption Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE This chapter describes the low-power consumption mode of the MB90330 series. 6.1 Outline of Low-Power Consumption Mode 6.2 Block Diagram of Low-power Consumption Control Circuit 6.3 Low-power Consumption Mode Control Register (LPMCR) 6.4 CPU Intermittent Operation Mode 6.5 Standby Mode 6.6 State Transition Diagram 6.7 State of the Pin during Standby Mode, Hold, and Reset...
Page 158: Outline Of Low-Power Consumption Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE Outline of Low-Power Consumption Mode The MB90330 series have the following CPU operation modes by selecting the operation clock and operating the control of the clock. • Clock mode (PLL clock mode, main clock mode, and sub clock mode) •...
Page 159 CHAPTER 6 LOW-POWER CONSUMPTION MODE Clock Mode PLL clock mode In PLL clock mode, the CPU and peripheral function operate on a PLL multiplying clock of oscillation clock (HCLK). Note: When using USB Mini-HOST and the USB function, you need to set to the PLL clock mode. Main clock mode In main clock mode, the CPU and peripheral function operate on a clock with 2-frequency division of oscillation clock (HCLK).
Page 160 CHAPTER 6 LOW-POWER CONSUMPTION MODE Sub sleep mode The sub-sleep mode terminates the CPU operation clock in the sub clock mode and operates components except for the CPU under the sub clock. Timebase timer mode The timebase timer mode terminates all the operations other than the oscillation clock, the timebase timer, and the clock timer, terminating all the functions other than the timebase timer and the watch timer.
Page 161: Block Diagram Of Low-Power Consumption Control Circuit
CHAPTER 6 LOW-POWER CONSUMPTION MODE Block Diagram of Low-power Consumption Control Circuit The low-power consumption control circuit is composed of the following seven blocks. • CPU intermittent operation selector • Standby controller circuit • CPU clock controller circuit • Peripheral clock controller circuit •...
Page 162 CHAPTER 6 LOW-POWER CONSUMPTION MODE CPU intermittent operation selector The CPU intermittent operation sector selects the number of the suspended clocks in the CPU intermittent operation mode. Standby controller circuit The standby controller circuit controls the CPU clock control circuit and the peripheral clock control circuit, and then performs the transition to the low-power consumption mode or cancellation.
Page 163: Low-Power Consumption Mode Control Register (Lpmcr)
CHAPTER 6 LOW-POWER CONSUMPTION MODE Low-power Consumption Mode Control Register (LPMCR) The low-power consumption mode control register (LPMCR) performs transition to/ cancellation of the low-power consumption mode or sets the number of the CPU clock suspend cycles in the CPU intermittent operation mode. Low-power Consumption Mode Control Register (LPMCR) Figure 6.3-1 shows the configuration of the low-power consumption mode control register (LPMCR).
Page 164 CHAPTER 6 LOW-POWER CONSUMPTION MODE Table 6.3-1 Function Description of Each Bit of Low-power Consumption Mode Control Register (LPMCR) Bit name Functions • This bit indicates the transition to the stop mode. • Writing "1" to this bit changes the stop mode. STP: •...
Page 165 CHAPTER 6 LOW-POWER CONSUMPTION MODE Access to Low-power Consumption Mode Control Register Transition to the low-power consumption modes (stop mode, sleep mode, timebase timer mode, and watch mode) by writing to the low-power consumption mode control register is made, in this case, be sure to use the instructions in Table 6.3-2.
Page 166: Cpu Intermittent Operation Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE CPU Intermittent Operation Mode The CPU intermittent operation mode is a mode for reducing the power consumption by intermittently operating the CPU while operating the external bus and peripheral functions at high speed. CPU Intermittent Operation Mode The CPU intermittent operation mode is a mode for stopping the clock supplied to the CPU for a predetermined period of time for each instruction execution to delay the internal bus cycle start when accessing the registers, internal memory (ROM, RAM), I/O, peripheral functions, or external bus.
Page 167: Standby Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE Standby Mode Standby modes are: sleep (PLL sleep, main sleep, sub-sleep), watch, timebase timer, and stop mode. Operation Status in Standby Mode Table 6.5-1 shows the operation state in the standby mode. Table 6.5-1 Operation Status in Standby Mode Transition Main Machine...
Page 168: Sleep Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5.1 Sleep Mode Sleep mode is mode for stopping the CPU operation clock and the operation other than CPU continues. When you instruct the transition to the sleep mode with the low-power consumption mode control register (LPMCR), the transition to the PLL sleep mode is made if the PLL clock mode is set, the transition to the main sleep mode is made if the main clock mode is set, and the transition to the sub sleep mode is made if the sub clock mode is set.
Page 169 CHAPTER 6 LOW-POWER CONSUMPTION MODE Cancellation of Sleep Modes The low-power consumption control circuit clears sleep mode by reset input or interrupt generation. Return by reset Initialization to the main clock mode is made by reset. Return by interrupt If there is an interrupt request higher than level 7 from the peripheral circuit and others in the sleep mode, the sleep mode is canceled.
Page 170: Timebase Timer Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5.2 Timebase Timer Mode The timebase timer mode terminates the original oscillation and all the operations other than the timebase timer and the watch timer, resulting in termination of all the functions other than the timebase timer and the watch timer. Transition to Timebase Timer Mode In the PLL clock mode or the main clock mode (the sub clock display bit (SCM)=1 of the clock selection register (CKSCR)), writing "0"...
Page 171 CHAPTER 6 LOW-POWER CONSUMPTION MODE Cancellation of Timebase Timer Modes The low-power consumption circuit cancels the timebase timer mode by generating a reset input or an interrupt request. Return by external reset The external reset initializes the mode to the main clock mode. Return by interrupt If there is an interrupt request higher than level 7 from peripheral circuit and others in the timebase timer mode (except for IL2, IL1, IL0 of the interrupt control register (ICR) = "111...
Page 172: Watch Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5.3 Watch Mode The watch mode terminates all the operations other than the sub clock and the watch timer, where almost all the functions of the chip are terminated. Transition to Watch Mode In the sub clock mode (the sub clock display bit of the clock selection register (CKSCR) (SCS)=0), when you write "0"...
Page 173 CHAPTER 6 LOW-POWER CONSUMPTION MODE Note: When handling an interrupt, the CPU usually services the interrupt after executing the instruction that follows the one specifying the watch mode. However, if the transition to the watch mode and the receipt of the external bus hold request occur at the same time, transition to interruption procedure may be made before execution of the next instruction.
Page 174: Stop Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5.4 Stop Mode Stop mode is mode for stopping original oscillation and all functions are stopped. That means, data can be held with the lowest power consumption. Transition to Stop Mode If you write "1" into the stop mode bit (STP) of the low-power consumption mode control register (LPMCR), the transition to the stop mode is made.
Page 175 CHAPTER 6 LOW-POWER CONSUMPTION MODE Notes: • When handling an interrupt, the CPU usually services the interrupt after executing the instruction that follows the one specifying the stop mode. When transition to stop mode and acceptance of an external bus hold request have occurred at the same time, interrupt processing may transit before executing the next instruction.
Page 176: State Transition Diagram
CHAPTER 6 LOW-POWER CONSUMPTION MODE State Transition Diagram The transition of the operation state and the transition conditions of MB90330 series are shown. State Transition Diagram Figure 6.6-1 shows the transition of the operation state and the transition conditions of MB90330 series. Figure 6.6-1 State Transition and Transition Conditions External reset, Watchdog timer reset, Software reset Power on...
Page 177 CHAPTER 6 LOW-POWER CONSUMPTION MODE Operation Status in Low-power Consumption Mode Table 6.6-1 lists the operation states in low-power consumption mode. Table 6.6-1 Operation States in Low-power Consumption Mode Main Timebase Clock Operating State Peripheral Clock Clock Clock Clock Timers Source Operation Operation...
Page 178: State Of The Pin During Standby Mode, Hold, And Reset
CHAPTER 6 LOW-POWER CONSUMPTION MODE State of the Pin during Standby Mode, Hold, and Reset The state of the pin at the time of the stand by mode, the hold, or the reset is shown for each memory access code. Pin State in Single-chip Mode Table 6.7-1 shows the state of the pin in the single-chip mode.
Page 179 CHAPTER 6 LOW-POWER CONSUMPTION MODE *3: "Input shutoff" indicates the state in which operation of the input gate nearest to the pin is inhibited. "Output Hi-Z" means that the pin is placed at high impedance with the pin driving transistor placed in the drive disabled state. *4: When operation stops due to a cause in the USB, the signal is input via the USB port.
Page 180 CHAPTER 6 LOW-POWER CONSUMPTION MODE Pin State in External Bus 16-bit Data Bus and Multiplex 16-bit External Bus Mode Table 6.7-2 shows the state of the pins of the external bus 16-bit data bus mode and the multiplex 16-bit external bus mode. Table 6.7-2 Pin State in External Bus 16-bit Data Bus and Multiplex 16-bit External Bus Mode In stop mode Pin Name...
Page 181 CHAPTER 6 LOW-POWER CONSUMPTION MODE *2: "Output enabled" means that the contents of operation appear via the pin because the pin driving transistor is in driven state and operation of the internal circuit remains enabled. *3: Same as the other ports if this is being used for the output state. "Input enabled" means that the input function is currently enabled;...
Page 182 CHAPTER 6 LOW-POWER CONSUMPTION MODE Pin State in External Bus 8-bit Data Bus and Multiplex 8-bit External Bus Mode Table 6.7-3 shows the state of the pins of the external bus 8-bit data bus mode and the multiplex 8-bit external bus mode. Table 6.7-3 Pin Signal State in External Bus 8-bit Data Bus and Multiplex 8-bit External Bus Mode In stop mode Pin Name...
Page 183 CHAPTER 6 LOW-POWER CONSUMPTION MODE *2: "Output enabled" means that the contents of operation appear via the pin because the pin driving transistor is in driven state and operation of the internal circuit remains enabled. *3: Same as the other ports if this is being used for the output state. "Input enabled" means that the input function is currently enabled;...
Page 184 CHAPTER 6 LOW-POWER CONSUMPTION MODE Pin State in External Bus 16-bit Data Bus and Non-multiplex 16-bit External Bus Mode Table 6.7-4 shows the state of the pins of the external bus 16-bit data bus mode and the non-multiplex 16- bit external bus mode. Table 6.7-4 Pin State in External Bus 16-bit Data Bus and Non-multiplex 16-bit External Bus Mode In stop mode Pin Name...
Page 185 CHAPTER 6 LOW-POWER CONSUMPTION MODE *3: Same as the other ports if this is being used for the output state. "Input enabled" means that the input function is currently enabled; Pull-up/Pull-down or an input from the external is required. *4: If this is being used as an output port, it holds the preceding value. *5: Outputs the initial output preceding this mode.
Page 186 CHAPTER 6 LOW-POWER CONSUMPTION MODE Pin State in External Bus 8-bit Data Bus and Non-multiplex 8-bit External Bus Mode Table 6.3-2 shows the state of the pins of the external bus 8-bit data bus mode and the non-multiplex 8-bit external bus mode. Table 6.7-5 Pin State in External Bus 8-bit Data Bus and Non-multiplex 8-bit External Bus Mode In stop mode Pin Name...
Page 187 CHAPTER 6 LOW-POWER CONSUMPTION MODE *2: "Output enabled" means that the contents of operation appear via the pin because the pin driving transistor is in driven state and operation of the internal circuit remains enabled. *3: Same as the other ports if this is being used for the output state. "Input enabled" means that the input function is currently enabled;...
Page 188: Precautions When Using Low-Power Consumption Mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE Precautions when Using Low-power Consumption Mode Special attention for the following is needed when using the low-power consumption mode. • Transition to standby mode and interrupt • Cancellation of standby mode by interrupt • Oscillation stabilization wait time •...
Page 189 CHAPTER 6 LOW-POWER CONSUMPTION MODE Oscillation Stabilization Wait Time Oscillation Stabilization Wait Time of oscillation clock Because the oscillator for original oscillation is stopped in stop mode, the oscillation stabilization wait time must be required. For the oscillation stabilization wait time, you take the time selected in the oscillation stabilization wait time selection bit (WA1, WA0) of the clock selection register (CKSCR).
Page 190 CHAPTER 6 LOW-POWER CONSUMPTION MODE Notes on Accessing the Low-Power Consumption Mode Control Register (LPMCR) to Enter the Standby Mode To access the low-power consumption mode control register (LPMCR) with assembler language • To set the low-power consumption mode control register (LPMCR) to enter the standby mode, use the instruction listed in Table 6.3-2.
Page 191: Chapter 7 Mode Setting
CHAPTER 7 MODE SETTING This chapter describes the mode setting and the external memory access. 7.1 Mode Setting 7.2 Mode Pins (MD2 to MD0) 7.3 Mode Data 7.4 External Memory Access 7.5 Operation in Each Mode of Mode Setting...
Page 192: Mode Setting
CHAPTER 7 MODE SETTING Mode Setting MC-16LX has respective modes in the access method, access area, and test. Respective mode is set according to the mode pin at the time of reset and the mode- fetched mode data. Mode Setting MC-16LX has respective modes in the access method, the access area, and the test, and Figure 7.1-1 shows the classification.
Page 193: Mode Pins (Md2 To Md0)
CHAPTER 7 MODE SETTING Mode Pins (MD2 to MD0) The mode pin is the three external pins (MD2 to MD0) and specifies the load methods for the reset vector and the mode data. Setting of Mode Pins (MD2 to MD0) With the mode pin (MD2 to MD0), you may select either the external data bus or the internal data bus for the reset vector read and select the bus width while selecting the external data bus.
Page 194: Mode Data
CHAPTER 7 MODE SETTING Mode Data The mode data is located on the memory of the "FFFFDF " address and specifies the operation after the reset sequence. The mode data is automatically taken into the CPU by a mode fetch. Mode Data While executing the reset sequence, the mode data in the "FFFFDF "...
Page 195 CHAPTER 7 MODE SETTING Set Bit of Bus Mode (M1,M0) The M1and M0 bits specify the operation mode after the reset sequence. Table 7.3-2 shows the content of the M1, M0 bit setting. Table 7.3-2 Content of M1 and M0 Bit Setting Function Single-chip mode Internal ROM external bus modes...
Page 196 CHAPTER 7 MODE SETTING Relation between Mode Pin and Mode Data (Recommended Example) Table 7.3-3 shows the relation between the mode pin and the mode data. Table 7.3-3 Relation between Mode Pin and Mode Data Mode Single Chip Internal ROM external bus mode 8 bits (Address data multiplex) Internal ROM external bus Mode 16 bits (Address data multiplex)
Page 197 CHAPTER 7 MODE SETTING Operation of External Pin in Each Mode Table 7.3-4 shows the operation relation of each external pin in the non-multiplex mode and the multiplex mode. Table 7.3-4 Operation Relation of External Pin in Each Mode Functions Non- multiplex mode Multiplex mode External Address control...
Page 198: External Memory Access
CHAPTER 7 MODE SETTING External Memory Access The block diagram of the external memory access, the configuration/function of the register, and the operation of the external memory access are described. I/O Signal Terminal of External Memory Access MC-16LX provides the following address/data/control signal to access the external memory/peripheral. •...
Page 199 CHAPTER 7 MODE SETTING Register List Figure 7.4-2 shows the list of the registers of the external bus pin control circuit. Figure 7.4-2 List of the Registers of External Bus Pin Control Circuit Automatic Ready Function 0000A5 Selection Register (ARSR) HMR1 HMR0 LMR1 LMR0 Reserved...
Page 200: Automatic Ready Function Selection Register (Arsr)
CHAPTER 7 MODE SETTING 7.4.1 Automatic Ready Function Selection Register (ARSR) The configuration and functions of the automatic ready function selection register (ARSR) are described. Automatic Ready Function Selection Register (ARSR) Figure 7.4-3 shows the bit configuration of the automatic ready function selection register (ARSR). Figure 7.4-3 Bit Configuration of automatic Ready Function Selection Register (ARSR) Automatic Ready Function 0000A5...
Page 201: External Address Output Control Register (Hacr)
CHAPTER 7 MODE SETTING 7.4.2 External Address Output Control Register (HACR) The configuration and functions of the external address output control register are described. External Address Output Control Register (HACR) Figure 7.4-4 shows the bit configuration of the external address output control register. Figure 7.4-4 Bit Configuration of External Address Output Control Register (HACR) External Address Output 0000A6...
Page 202: Bus Control Signal Selection Register (Epcr)
CHAPTER 7 MODE SETTING 7.4.3 Bus Control Signal Selection Register (EPCR) The configuration and functions of the bus control signal selection register are described. Bus Control Signal Selection Register (EPCR) The bus control signal selection register sets the control functions of the bus operation in the external bus mode.
Page 203 CHAPTER 7 MODE SETTING [bit 11] HMBS Specify the bus size when accessing the external bus to the area 800000 to FFFFFF in the external data bus 16-bit mode. Bus size access of 16 bits (Initial Value in the external vector mode 1) Bus size access of 8 bits (Initial Value in the external vector mode 0.2) [bit 10] WRE Control the output of the external write signal (WRH/WRL) pins in the external data bus 16-bit mode, and...
Page 204: Operation In Each Mode Of Mode Setting
CHAPTER 7 MODE SETTING Operation in Each Mode of Mode Setting Operation in each mode of mode setting is described in the timing chart. Mode Type Operations of the following items are described for each function. • External memory access control signal - External data bus 8-bit mode (non-multiplex mode) - External data bus 8-bit mode (multiplex mode) - External data bus 16-bit mode (non-multiplex mode)
Page 205: External Memory Access Control Signal
CHAPTER 7 MODE SETTING 7.5.1 External Memory Access Control Signal The access to the external memory is performed at 3 cycles unless the ready function is not used. External Memory Access Control Signal Figure 7.5-1 to Figure 7.5-4 show the timing charts of the external access in each mode. The 8-bit bus width access in the external data bus 16-bit mode reads or writes the 8-bit width peripheral chip when you connect to the external bus by mixing the 8-bit width peripheral chip and the 16-bit width peripheral chip.
Page 206 CHAPTER 7 MODE SETTING External Data Bus 8-Bit Mode (External Data Bus 8-Bit/Multiplex Mode) Figure 7.5-2 Timing Chart of External Memory Access (Multiple Mode) Read Write Read P57/CLK P53/WRH (Port data) P52/WRL P51/RD P50/ALE Read address Write address Read address A23 to A16 (Port data) A15 to A08...
Page 207 CHAPTER 7 MODE SETTING External 16-Bit Bus Mode (External Data Bus 16-Bit/Multiplex Mode) Figure 7.5-4 Timing Chart of External Memory Access (External Data Bus 16-bit/multiplex Mode) Read Write Read P57/CLK P53/WRH P52/WRL P51/RD P50/ALE Read address Write address A23 to A16 Read address (Port data) A15 to A08...
Page 208: Ready Function
CHAPTER 7 MODE SETTING 7.5.2 Ready Function The setting of the P56/RDY pin or the automatic ready function selection register (ARSR) enables the access to the low-speed memory and the peripheral circuits. When the RYE bit in the bus control signal selection register (EPCR) is set to "1", the condition is in the wait cycle while the period "L"...
Page 209 CHAPTER 7 MODE SETTING Non-multiplex mode Figure 7.5-5 Timing Chart of Ready Function (Non-multiplex Mode) Even address word read Odd address word write P57/CLK P53/WRH P52/WRL P51/RD P50/ALE A23 to A16 Write address Read address Read address Write address A15 to A08 Read address Write address A07 to A00...
Page 210 CHAPTER 7 MODE SETTING Multiplex mode Figure 7.5-6 Timing Chart of Ready Function (Multiplex Mode) Even address word read Odd address word write P57/CLK P53/WRH P52/WRL P51/RD P50/ALE Write address Read address A23 to A16 (Port data) A15 to A08 A07 to A00 (Port data) D15 to D08/...
Page 211: Holding Function
CHAPTER 7 MODE SETTING 7.5.3 Holding Function The operation of the hold function is described in the timing chart. Operation of Holding Function If the HDE bit in the EPCR is set to "1", the hold function of the external bus by both the P54/HRQ and the P55/HAK pins are enabled.
Page 212 CHAPTER 7 MODE SETTING Figure 7.5-7 Timing Chart of Holding Function (Non-multiplex Mode) Read cycle Hold cycle Write cycle P57/CLK P54/HRQ P55/HAK P53/WRH P52/WRL P51/RD P50/ALE (Address) (Address) A23 to A16 (Address) (Address) A15 to A08 (Address) (Address) A07 to A00 D15 to D08/ AD15 to AD08 D07 to D00/...
Page 213: Chapter 8 I/O Port
CHAPTER 8 I/O PORT This chapter describes the configuration and functions of the register used in the I/O port. 8.1 Functions of I/O Ports 8.2 I/O Port Register...
Page 214: Functions Of I/O Ports
CHAPTER 8 I/O PORT Functions of I/O Ports The overview of functions of the I/O ports is shown. Functions of I/O Ports The I/O port outputs data from the CPU to the I/O pin and loads the signal input in the I/O pin in the CPU by using the port data register (PDR).
Page 215: I/O Port Register
CHAPTER 8 I/O PORT I/O Port Register The configuration and functions of the register used in the I/O port are described. I/O Port Registers There are the following registers in I/O port. • Port data register (PDR0 to PDRB) • Port direction register (DDR0 to DDRB) •...
Page 216: Port Data Register (Pdr0 To Pdrb)
CHAPTER 8 I/O PORT 8.2.1 Port Data Register (PDR0 to PDRB) The configuration and functions of the port data register (PDR0 to PDRB) are described. Port Data Register (PDR0 to PDRB) Figure 8.2-1 shows the list of the port data register (PDR0 to PDRB). Figure 8.2-1 List of Port Data Register (PDR0 to PDRB) Initial value Access...
Page 217: Port Direction Register (Ddr0 To Ddrb)
CHAPTER 8 I/O PORT 8.2.2 Port Direction Register (DDR0 to DDRB) The configuration and functions of the port direction register are described. Port Direction Register (DDR0 to DDRB) Figure 8.2-2 shows the list of the port direction register (DDR0 to DDRB). Figure 8.2-2 List of Port Direction Register (DDR0 to DDRB) Initial value Access...
Page 218: Other Registers
CHAPTER 8 I/O PORT 8.2.3 Other Registers The configuration and functions of the register other than the port data register (PDR0 to PDRB) and the port direction register (DDR0 to DDRB) are described. Port 0,1 Pull-up Resistance Register (RDR0,RDR1) Figure 8.2-3 shows the bit configuration of the pull-up resistance register (RDR0, RDR1). Figure 8.2-3 Bit Configuration of Pull-up Resistance Register (RDR0,RDR1) Initial value Access...
Page 219 CHAPTER 8 I/O PORT Analog Input Enable Register (ADER0,ADER1) Figure 8.2-5 shows the bit configuration of the analog input permission registers (ADER0, ADER1). Figure 8.2-5 Bit Configuration of analog Input Enable Register (ADER0, ADER1) Initial value Access ADER0 11111111 00001E Address : ADE07 ADE06 ADE05 ADE04 ADE03 ADE02 ADE01 ADE00 ADER1...
Page 220 CHAPTER 8 I/O PORT...
Page 221: Chapter 9 Timebase Timer
CHAPTER 9 TIMEBASE TIMER This chapter describes the function and operation of the timebase timer. 9.1 Overview of Timebase Timer 9.2 Configuration of Timebase Timer 9.3 Timebase Timer Control Register (TBTC) 9.4 Interrupt of Timebase Timer 9.5 Operations of Timebase Timer 9.6 Precautions when Using Timebase Timer 9.7 Program Example of Timebase Timer...
Page 222: Overview Of Timebase Timer
CHAPTER 9 TIMEBASE TIMER Overview of Timebase Timer The timebase timer has an interval timer function that enables a selection of four interval times using 18-bit free-run counter (timebase counter) count-up with synchronizing to the internal count clock (2 division of original oscillation). Furthermore, the function of timer output of oscillation stabilization wait time or function supplying operation clocks for watchdog timer are provided.
Page 223 CHAPTER 9 TIMEBASE TIMER Function of Clock Supply The clock supply function supplies the operating clock to the timer for oscillation stabilization wait time and some peripheral functions. Table 9.1-2 shows the clock cycle supplied from the timebase timer to each peripheral.
Page 224: Configuration Of Timebase Timer
CHAPTER 9 TIMEBASE TIMER Configuration of Timebase Timer The timebase timer consists of the following four blocks. • Timebase timer counter • Counter clear circuit • Interval timer selector • Timebase timer control register (TBTC) Block Diagram of Timebase Timer Figure 9.2-1 shows the block diagram of the timebase timer.
Page 225 CHAPTER 9 TIMEBASE TIMER Counter clear circuit This circuit clears the counter by writing "0" to timebase timer initialization bit (TBR) of timebase timer control register (TBTC), power-on reset, transition to the stop mode, switching to PLL clock mode from the main clock mode or sub clock, or switching to the main clock mode from sub clock.
Page 226: Timebase Timer Control Register (Tbtc)
CHAPTER 9 TIMEBASE TIMER Timebase Timer Control Register (TBTC) The timebase timer control register (TBTC) executes interval time selection, timebase timer counter clearance, and interrupt control and status check. Timebase Timer Control Register (TBTC) Figure 9.3-1 Timebase Timer Control Register (TBTC) Address bit15 bit14 bit13 bit12 bit11 bit10 bit7...
Page 227 CHAPTER 9 TIMEBASE TIMER Table 9.3-1 Timebase Timer Control Register (TBTC) Bit name Functions Reserved: Note: bit 15 Reserved bit Be sure to write "1". • The value at the time of reading is irregular. bit 14 Unused bits • No effect on writing. bit 13 •...
Page 228: Interrupt Of Timebase Timer
CHAPTER 9 TIMEBASE TIMER Interrupt of Timebase Timer The timebase timer can generate an interrupt request by the overflow of the specified bit of the timebase timer counter (interval timer function). Interrupt of Timebase Timer After the timebase counter undergoes count-up with the internal count clock and the bit for the selected interval timer overflows, the interrupt request flag bit (TBOF) of timebase timer control register (TBTC) is set to "1".
Page 229: Operations Of Timebase Timer
CHAPTER 9 TIMEBASE TIMER Operations of Timebase Timer The timebase timer has functions of interval timer and clock supply to peripheral functions. Operation of Interval Timer Function (Timebase Timer) Interval timer function generates interrupt requests at regular intervals. In order to function as an interval timer, setup in Figure 9.5-1 is needed.
Page 230 CHAPTER 9 TIMEBASE TIMER Table 9.5-1 Timebase Timer Counter Clearance Operation and Oscillation Stabilization Wait Time Operation Counter TBOF Oscillation Stabilization Wait Time Clear Writing "0" to timebase timer initialization bit (TBR) of timebase timer control register (TBTC) Power-on reset Watchdog reset Main clock oscillation stabilization wait time Release of main stop mode...
Page 231: Precautions When Using Timebase Timer
CHAPTER 9 TIMEBASE TIMER Precautions when Using Timebase Timer Cautions about influences on peripheral functions due to interrupt request and timebase timer clearances. Precautions when Using Timebase Timer Clearing Interrupt request When clearing the interrupt request flag bit (TBOF) in the timebase timer control register (TBTC), perform while the timebase timer interrupt is masked by the setting of the interrupt level mask register (IML) of the interrupt request permission bit (TBIE) or the processor status (PS).
Page 232 CHAPTER 9 TIMEBASE TIMER Operations of Timebase Timer Operations in the following situations are shown in Figure 9.6-1. • At a power-on reset occurs. • At a transition to sleep mode during the operation of interval timer function • At a transition to stop mode. •...
Page 233: Program Example Of Timebase Timer
CHAPTER 9 TIMEBASE TIMER Program Example of Timebase Timer Programming examples for the timebase timer are shown below. Program Example of Timebase Timer Processing specification Interval interruptions of 2 /HCLK (oscillation clock) are repeatedly generated. In this case, the interval time is about 0.68 ms (at 6-MHz operation).
Page 234 CHAPTER 9 TIMEBASE TIMER 0FF6CH ; The interruption vector is set WARI 0FFDCH ; Reset vector setting START ; Single-chip mode VECT ENDS START...
Page 235: Chapter 10 Watchdog Timer
CHAPTER 10 WATCHDOG TIMER This chapter describes the function and operation of the watchdog timer. 10.1 Overview of Watchdog Timer 10.2 Watchdog Timer Control Register (WDTC) 10.3 Configuration of Watchdog Timer 10.4 Operations of Watchdog Timer 10.5 Precautions when Using Watchdog Timer 10.6 Program Examples of Watchdog Timer...
Page 236: Overview Of Watchdog Timer
CHAPTER 10 WATCHDOG TIMER 10.1 Overview of Watchdog Timer The watchdog timer is a 2-bit counter operating with an output of the timebase timer or clock timer as the count clock and resets the CPU when the counter is not cleared for a preset period of time.
Page 237 CHAPTER 10 WATCHDOG TIMER Reference: When the watchdog timer is activated, it is initialized and set to the stopped state by a reset upon power-on or by a reset by the watchdog. Also, the watchdog counter is cleared by writing to the reset by the external pin, the software reset, and the watchdog control bit (WTE) of the watchdog timer control register and by changing to sleep, stop, and watch mode, but the watchdog timer is still activated.
Page 238: Watchdog Timer Control Register (Wdtc)
CHAPTER 10 WATCHDOG TIMER 10.2 Watchdog Timer Control Register (WDTC) The watchdog timer control register (WDTC) displays the activation, clearance, and reset factor of the watchdog timer. Watchdog Timer Control Register (WDTC) Figure 10.2-1 shows the watchdog timer control register (WDTC). Table 10.2-1 describes the function of each bit of the WDTC register.
Page 239 CHAPTER 10 WATCHDOG TIMER Table 10.2-1 Function of Each Bit of Watchdog Timer Control Register (WDTC) Bit name Functions • Read-only bits that indicate reset factors. When a reset factor occurs, the relevant bit is set to "1". bit 7 PONR •...
Page 240: Configuration Of Watchdog Timer
CHAPTER 10 WATCHDOG TIMER 10.3 Configuration of Watchdog Timer The watchdog timer consists of following five blocks. • Count clock selector • Watchdog counter (two bits counter) • Watchdog reset generator circuit • Counter clear control circuit • Watchdog timer control register (WDTC) Block Diagram of Watchdog Timer Figure 10.3-1 shows a watchdog timer block diagram.
Page 241 CHAPTER 10 WATCHDOG TIMER Counter clear control circuit Clears the watchdog counter and controls operation/stop of the counter. Watchdog timer control register (WDTC) Activates/clears the watchdog timer and holds the reset occurrence factor.
Page 242: Operations Of Watchdog Timer
CHAPTER 10 WATCHDOG TIMER 10.4 Operations of Watchdog Timer The watchdog timer generates a watchdog reset upon an overflow of the watchdog counter. Operations of Watchdog Timer Figure 10.4-1 shows the setting required to operate the watchdog timer. Figure 10.4-1 Setting of Watchdog Timer bit15 bit8 Address...
Page 243 CHAPTER 10 WATCHDOG TIMER Figure 10.4-2 Relationship between Clear Timing and Interval Time of Watchdog Timer [Block diagram of Watchdog timer] 2-bit counter Reset 2 divided 2 divided Clock selector Reset circuit signal circuit circuit Count enable and clear Count enable output circuit WTE bit [Minimum interval time]...
Page 244: Precautions When Using Watchdog Timer
CHAPTER 10 WATCHDOG TIMER 10.5 Precautions when Using Watchdog Timer This section explains precautions when using watchdog timer. Precautions when Using Watchdog Timer Stopping watchdog timer Once the watchdog time is activated, it cannot stop until power-on or a watchdog-external reset occurs. Interval Time Because the interval time uses carry-up signals from the timebase timer, as the count clock, clearing the timebase timer may make the interval time of the watch dog timer longer than the preset period of time.
Page 245: Program Examples Of Watchdog Timer
CHAPTER 10 WATCHDOG TIMER 10.6 Program Examples of Watchdog Timer Program example of watchdog timer is given below. Program Examples of Watchdog Timer Processing specification • The watchdog timer is cleared each time in loop of the main program. • The processing of the main loop must go round within the minimum interval time. Coding example WDTC 0000A8H...
Page 246 CHAPTER 10 WATCHDOG TIMER...
Page 247: Chapter 11 Watch Timer
CHAPTER 11 WATCH TIMER This chapter describes a overview of the watch timer, functions and configurations of its registers, and its operation. 11.1 Overview of Watch Timer 11.2 Configuration of Watch Timer 11.3 Watch Timer Control Register (WTC) 11.4 Operation of Watch Timer...
Page 248: Overview Of Watch Timer
CHAPTER 11 WATCH TIMER 11.1 Overview of Watch Timer The watch timer is a 15-bit timer using the sub clock. It can generate interval interrupts. The watch timer can also be used as the clock source of the watchdog timer by setting Functions of Watch Timer The watch timer consists of a 15-bit timer and a circuit that controls interval interrupt.
Page 249: Configuration Of Watch Timer
CHAPTER 11 WATCH TIMER 11.2 Configuration of Watch Timer The watch timer is composed of the following four blocks. • Interval selector • Watch Counter • Watch timer interruption generation circuit • Watch timer control register (WTC) Block Diagram of Watch Timer Figure 11.2-1 shows the watch timer block diagram.
Page 250: Watch Timer Control Register (Wtc)
CHAPTER 11 WATCH TIMER 11.3 Watch Timer Control Register (WTC) Watch timer control register (WTC) controls the operation of watch timer. It also controls the interval interrupt time. Configuration of Watch Timer Control Register (WTC) Figure 11.3-1 shows the watch timer control register (WTC) configuration. Table 11.3-1 summarizes the functions of each bit functions of watch timer control register (WTC).
Page 251 CHAPTER 11 WATCH TIMER Table 11.3-1 Each Bit Functions of Watch Timer Control Register (WTC) Bit name Functions • This bit selects the clock source of the watchdog timer. WDCS: • Watch timer clock is selected if this bit is "0", and otherwise timebase timer clock is bit 7 Watchdog timer clock selected if this bit is "1".
Page 252: Operation Of Watch Timer
CHAPTER 11 WATCH TIMER 11.4 Operation of Watch Timer The watch timer functions as s clock source for the watchdog timer, a timer for sub clock oscillation stabilization delay time and an interval timer that generates an interrupt at regular intervals. Watch Counter The watch counter is a 15-bit counter that counts sub clock and continues counting while sub clock is input.
Page 253 CHAPTER 12 16-BIT I/O TIMER This chapter describes a overview of the 16-bit I/O timer, the functions and configurations of its registers, and its operation. 12.1 Overview of 16-bit I/O Timer 12.2 Register of 16-bit I/O Timer 12.3 Operation of 16-bit I/O Timer...
Page 254: Chapter 12 16-Bit I/O Timer
CHAPTER 12 16-BIT I/O TIMER 12.1 Overview of 16-bit I/O Timer The 16-bit I/O timer consists of one 16-bit free-run timer, and four output compare and four input capture modules. This function enables four independent waveforms to be output based on the 16-bit free-run timer, and input pulse widths and external clock cycle to be measured.
Page 255 CHAPTER 12 16-BIT I/O TIMER Block Diagram Figure 12.1-1 shows the 16-bit I/O timer block diagram. Figure 12.1-1 Block Diagram of 16-bit I/O Timer Control logic Interrupt to each blocks 16-bit free-run timer 16-bit timer Clear Output compare 0 OUT0 Compare register 0 Output compare 1 OUT1...
Page 256: Register Of 16-Bit I/O Timer
CHAPTER 12 16-BIT I/O TIMER 12.2 Register of 16-bit I/O Timer Registers for the 16-bit I/O timer are classified into the following general categories: • 16-bit free-run timer • 16-bit output compare • 16 bit input capture The configuration and functions of register are described. Register Configuration of 16-bit I/O Timer The register configuration of the 16-bit I/O timer is shown in the following.
Page 257: 16-Bit Free-Run Timer
CHAPTER 12 16-BIT I/O TIMER 12.2.1 16-bit Free-run Timer The 16-bit free-run timer consists of a 16-bit up-down counter and control status register. A value of the timer counter is used as a basic time of the input capture and output compare (base timer).
Page 258 CHAPTER 12 16-BIT I/O TIMER Block Diagram of 16-bit Free-run Timer Figure 12.2-5 shows the 16-bit free-run timer block diagram. Figure 12.2-5 Block Diagram of 16-bit Free-run Timer φ Interrupt request #36 Comparator IVFE STOP MODE CLR CLK2 CLK1 CLK0 Clock 16-bit free-run timer Count value output T15 to T00...
Page 259 CHAPTER 12 16-BIT I/O TIMER Timer Counter Data Register (TCDT) Figure 12.2-7 shows the bit configuration of the timer counter data register (TCDT). Figure 12.2-7 Bit Configuration of Timer Counter Data Register (TCDT) TCDT Timer counter data register upper 000087 R/W R/W R/W R/W Initial value...
Page 260 CHAPTER 12 16-BIT I/O TIMER [bit 12 to bit 10] MSI2,MSI1,MSI0 (Interrupt mask selection bit) Bit to set the number of times the compare clear interrupt be masked. It consists of a 3-bit reload counter and the count value is reloaded every time the counter value is "000 ".
Page 261 CHAPTER 12 16-BIT I/O TIMER [bit 5] STOP (Timer operation stop bit) It is bit for stopping count of 16-bit free-run timer. Writing "1" into this bit stops counting the 16-bit free-run timer and writing "0" starts counting it. Count permission (operation) [Initial value] Count disabled (Stop) Note that the output compare operation will stop when the 16-bit free-run timer stops counting.
Page 262 CHAPTER 12 16-BIT I/O TIMER [bit 2 to bit 0] CLK2,CLK1,CLK0 (Count clock cycle selection bit) Select count clock of 16-bit free-run timer. Since the clock is changed immediately after writing into the CLK2, CLK1, and CLK0 bits you must change it when the output compare and input capture are in stopping state.
Page 263: Output Compare
CHAPTER 12 16-BIT I/O TIMER 12.2.2 Output Compare The output compare consists of 16-bit compare registers, compare output pin part, and a control register. It can reverse the output level for the pin and, at the same time, generate an interrupt when the 16-bit free-run timer value matches a value set in the 16- bit compare registers.
Page 264 CHAPTER 12 16-BIT I/O TIMER Block Diagram of Output Compare Figure 12.2-10 shows the output compare block diagram. Figure 12.2-10 Block Diagram of Output Compare Compare control OUT0,OUT2 OTE0 Compare register 0,2 CMOD 16-bit timer counter value (T15 to T00) OTE1 OUT1,OUT3 Compare control...
Page 265 CHAPTER 12 16-BIT I/O TIMER Output Compare Control Registers (OCS0 to OCS3) Figure 12.2-12 shows the bit configurations of the output compare control registers (OCS0 to OCS3). Figure 12.2-12 Bit Configurations of Output Compare Control Registers (OCS0 to OCS3) OCS1/OCS3 Output compare ch1:000055 control register upper...
Page 266 CHAPTER 12 16-BIT I/O TIMER [bit 9, bit 8] OTD1,OTD0 (Output level bit) It is used when you want to change the pin output level if the pin output of the output compare is enabled. The initial value of the compare pin output is "0". To perform a write operation, first, stop the compare operation.
Page 267 CHAPTER 12 16-BIT I/O TIMER Note: Since the output compare is synchronous with the clock of the 16-bit free-run timer, stopping the timer means the stop of the compare operation.
Page 268: Input Capture
CHAPTER 12 16-BIT I/O TIMER 12.2.3 Input Capture This module has a function that detects a rising edge, falling edge, or both edges of externally input signal and holds a value of the 16-bit free-run timer in a register at the time of detection.
Page 269 CHAPTER 12 16-BIT I/O TIMER List of Register of Input Capture Figure 12.2-14 lists input capture registers. Figure 12.2-14 List of Register of Input Capture IPCP0 to IPCP3 ch0:007911 Input capture data register upper CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 ch1:007913 Initial value XXXXXXXX...
Page 270 CHAPTER 12 16-BIT I/O TIMER Figure 12.2-16 The Configuration of Input Capture Control Status Register (ICS01,ICS23) ICS23 Input capture 000053 ICP3 ICP2 ICE3 ICE2 EG31 EG30 EG21 EG20 control status register 23 Initial value R/W R/W R/W R/W 00000000 ICS01 Input capture 000052 control status register 01...
Page 271: Operation Of 16-Bit I/O Timer
CHAPTER 12 16-BIT I/O TIMER 12.3 Operation of 16-bit I/O Timer The operation and timing of the 16-bit I/O timer are described. Operation and Timing of 16-bit I/O Timer The following items related to the operation and timing of the 16-bit I/O timer are described. •...
Page 272: Operation Of 16-Bit Free-Run Timer
CHAPTER 12 16-BIT I/O TIMER 12.3.1 Operation of 16-bit Free-run Timer The operation and timing of the 16-bit free-run timer are described. Operation of 16-bit Free-run Timer The 16-bit free-run timer starts counting at the counter value of "0000 " when a reset has been released. This counter value is a reference time for the 16-bit output compare and 16-bit input capture.
Page 273 CHAPTER 12 16-BIT I/O TIMER Figure 12.3-2 Timing Chart of Counter Clear by Comparison Result Agreement Counter value FFFF BFFF 7FFF 3FFF 0000 Time Reset Compare BFFF register value Interrupt...
Page 274: Operation Of 16-Bit Output Compare
CHAPTER 12 16-BIT I/O TIMER 12.3.2 Operation of 16-bit Output Compare The 16-bit output compare compares the value of the 16-bit free-run timer with that set in one of the compare registers, sets the interrupt request flag and, at the same time, reverses the output level when a match is detected.
Page 275 CHAPTER 12 16-BIT I/O TIMER Example of the output waveform by two pairs of compare registers Figure 12.3-4 shows an example of the output waveform when the output initial value is "0". Figure 12.3-4 Example of Output Waveform by Two Pairs of Compare Registers (for Output Initial Value= "0") Compare value FFFF...
Page 276: Operation Of 16-Bit Input Capture
CHAPTER 12 16-BIT I/O TIMER 12.3.3 Operation of 16-bit Input Capture The 16-bit input capture can capture the value of the 16-bit free-run timer into the capture register and generate an interrupt when it detects a predefined valid edge. Example of Taking Timing of Input Capture Figure 12.3-5 shows the input capture capturing timing example.
Page 277: Timing Of 16-Bit Free-Run Timer
CHAPTER 12 16-BIT I/O TIMER 12.3.4 Timing of 16-bit Free-run Timer The 16-bit free-run timer is counted up by the input clock (internal or external clock). When an external clock is selected, this timer is counted up at a rising edge. Count Timing of Free-run Timer Figure 12.3-6 shows the count timing for the free-run timer.
Page 278: Output Compare Timing
CHAPTER 12 16-BIT I/O TIMER 12.3.5 Output Compare Timing The output compare indicates that a compare match signal that is generated when the free-run timer match the value set in the compare registers can reverse the output value and raise an interrupt. The output inverse timing when a comparing match is detected is in sync with the counter timing.
Page 279: Input Timing Of Input Capture
CHAPTER 12 16-BIT I/O TIMER 12.3.6 Input Timing of Input Capture Capture timing to input signal of input capture is described. Capture Timing to Input Signal Figure 12.3-10 shows the capture timing to the input signal of the input capture. Figure 12.3-10 Capture Timing to Input Signal of Input Capture φ...
Page 280 CHAPTER 12 16-BIT I/O TIMER...
Page 281: Chapter 13 Usb Function
CHAPTER 13 USB FUNCTION This chapter describes the functions and overview of the USB Function. 13.1 Overview of USB Function 13.2 Block Diagram of USB Function 13.3 Register of USB Function 13.4 Operation Explanation of USB Function...
Page 282: Overview Of Usb Function
CHAPTER 13 USB FUNCTION 13.1 Overview of USB Function The USB Function is an interface that supports the USB (Universal Serial Bus) communication protocol. It operates supporting the transfer speed of FULL (12 Mbps) and has the following characteristics. Features of USB Function •...
Page 283: Block Diagram Of Usb Function
CHAPTER 13 USB FUNCTION 13.2 Block Diagram of USB Function Figure 13.2-1 shows the USB Function block diagram. Block Diagram of USB Function Figure 13.2-1 Block Diagram of USB Function EndPoint0 Internal In buffer data bus EndPoint0 Out buffer EndPoint1 buffer Interrupt #11,12...
Page 284: Register Of Usb Function
CHAPTER 13 USB FUNCTION 13.3 Register of USB Function The configuration and functions of registers used in the USB Function are described. Register List of USB Function Figure 13.3-1 Register List of USB Function UDCC (R/W) EP0C (R/W) EP1C (R/W) EP2C (R/W) EP3C...
Page 285 CHAPTER 13 USB FUNCTION Figure 13.3-2 Register of USB Function (1/2) Address:0000D0 RESUM HCON USTP Reserved Reserved RFBK UDC control register (UDCC) Address:0000D2 Reserved PKS0 EP0 control register (EP0C) Address:0000D3 Reserved Reserved Reserved Reserved Reserved Reserved STAL Reserved Address:0000D4 PKS 1 EP1 control register (EP1C) Address:0000D5 EPEN...
Page 286 CHAPTER 13 USB FUNCTION Figure 13.3-2 Register of USB Function (2/2) Address:0000E7 BFINI DRQIE SPKIE Reserved BUSY SIZE Address:0000E8 Reserved SIZE EP2 status register (EP2S) Address:0000E9 BFINI DRQIE SPKIE Reserved BUSY Reserved Address:0000EA Reserved SIZE EP3 status register (EP3S) Address:0000EB BFINI DRQIE SPKIE...
Page 287: Udc Control Register (Udcc)
CHAPTER 13 USB FUNCTION 13.3.1 UDC Control Register (UDCC) UDC control register (UDCC) controls the UDC core circuit. UDC Control Register (UDCC) Figure 13.3-3 shows the bit configuration of the UDC control register (UDCC). Figure 13.3-3 UDC Control Register (UDCC) Addressbit 0000D0 RESUM...
Page 288 CHAPTER 13 USB FUNCTION [bit 6] RESUM: Resume setting bit When it is in remote Wake-up enabled status (or DEVICE_REMOTE_WAKEUP bit is set with the SET_FEATURE command by the host) and in suspend status, the resume operation is started by writing 1 to the RESUM bit.
Page 289 CHAPTER 13 USB FUNCTION [bit 3, bit 2] Reserved bit It is reserved bit. Please write "0". The bit always reads "0". [bit 1] RFBK: Data toggle mode selection bit (rate feedback mode) It is a bit that selects data toggle mode for USB Interrupt transfer. RFBK Operating mode Selection of alternation data toggle mode...
Page 290: Ep0 Control Register (Ep0C)
CHAPTER 13 USB FUNCTION 13.3.2 EP0 Control Register (EP0C) EP0 control register (EP0C) controls concerning end point 0. EP0 Control Register (EP0C) Figure 13.3-4 shows the bit configuration of the EP0 control register (EP0C). Figure 13.3-4 EP0 Control Register (EP0C) Address 0000D2 Reserved...
Page 291 CHAPTER 13 USB FUNCTION [bit 8, bit 7] Reserved bit It is reserved bit. Please write "0". The bit always reads "0" when read. [bit 6 to bit 0] PKS0:Packet size end point 0 set bit It specifies the maximum number of transfer bytes per packet. The maximum number of transfer bytes per packet that EndPoint0 can specify is 64 bytes, which is a setting common to IN and OUT.
Page 292: Ep1 To Ep5 Control Register (Ep1C To Ep5C)
CHAPTER 13 USB FUNCTION 13.3.3 EP1 to EP5 Control Register (EP1C to EP5C) EP1 to EP5 control register (EP1C to EP5C) controls concerning end point 1 to 5. EP1 to EP5 Control Register (EP1C to EP5C) Figure 13.3-5 shows the bit configuration of the EP1C to EP5C control register (EP1C to EP5C). Figure 13.3-5 EP1 to EP5 Control Register (EP1C to EP5C) Address EP1C 0000D4...
Page 293 CHAPTER 13 USB FUNCTION [bit 15] EPEN: End Point 1 to 5 permission bit The end point is made effective. Setting the EPEN bit allows it to be configures by the host as an end point for use in the USB Function. TYPE, DIR, and PKS of the EP1 to EP5 control registers become valid for configuration information.
Page 294 CHAPTER 13 USB FUNCTION [bit 10] NULE: NULL automatic transfer enable bit This bit sets up a mode where the last packet transfer will be detected and 0-byte data transfer will be automatically sent when IN- direction data transfer request arrives if the automatic buffer transfer mode is set (DMAE=1).
Page 295: Time Stamp Register (Tmsp)
CHAPTER 13 USB FUNCTION 13.3.4 Time Stamp Register (TMSP) The time stamp register (TMSP) displays a frame number when an SOF packet is received. Time Stamp Register (TMSP) Figure 13.3-6 shows the bit configuration of the timestamp register (TMSP). Figure 13.3-6 Time Stamp Register (TMSP) Address bit 0000DE TMSP...
Page 296: Udc Status Register (Udcs)
CHAPTER 13 USB FUNCTION 13.3.5 UDC Status Register (UDCS) The UDC status register (UDCS) is a register that indicates the status of a bus on USB communications and a particular command received. Each bit in the register except SETP indicates an interrupt factor and raises an interrupt to CPU if its corresponding interrupt enable bit is specified and valid.
Page 297 CHAPTER 13 USB FUNCTION [bit 6] VON:VBUS connection detection bit The detection of USB cabling is shown. It is set if VBUS changes from being disconnected ("L" level kept detecting for not less than 2.6 µs) to 2.6µs continuous application of "H" level potential. The VON bit is a interrupt factor and writing "1"...
Page 298 CHAPTER 13 USB FUNCTION Note: Set registers again by initializing the USB Function with RST in the UDCC register when the BRST bit is detected. [bit 2] WKUP: Wake-Up detection bit It displays the fact that the USB Function has returned from suspend status. What causes the USB Function to return from suspend status are a remote wake-up by setting the RESUM bit and a wake-up from the host request, and the WKUP bit is automatically set only by a return request from the host.
Page 299 CHAPTER 13 USB FUNCTION [bit 0] CONF: Configuration detection bit It displays the fact that the USB Function has been configured. The CONF bit is set when a SetConfig, a USB command, has been successfully received. The CONF bit is an interrupt factor and writing "1" is ignored.
Page 300: Udc Interruption Enable Register (Udcie)
CHAPTER 13 USB FUNCTION 13.3.6 UDC Interruption Enable Register (UDCIE) The UDC interrupt enable register (UDCIE) is a register that allows each interrupt factor in the UDC status register to be raised as an interrupt bit wisely except CONFN. UDC Interruption Permission Register (UDCIE) Figure 13.3-8 shows the bit configuration of the UDC interrupt enable register (UDCIE).
Page 301 CHAPTER 13 USB FUNCTION [bit 12] SOFIE:SOF reception interruption permission bit It allows an interrupt due to the interrupt factor for the UDC status register "SOF" to be generated. SOFIE Operating mode Interrupt disabled by SOF factor Interruption permission by SOF factor [bit 11] BRSTIE: Bus reset interruption permission bit It allows an interrupt due to the interrupt factor for the UDC status register "BRST"...
Page 302: Ep0I Status Register (Ep0Is)
CHAPTER 13 USB FUNCTION 13.3.7 EP0I Status Register (EP0IS) The EP0I status register (EP0IS) displays status related to transfer toward In for EndPoint0. EP0I Status Register (EP0IS) Figure 13.3-9 shows the bit configuration of the EP0IS register (EP0IS). Figure 13.3-9 EP0I Status Register (EP0IS) Address 0000E2 Reserved...
Page 303 CHAPTER 13 USB FUNCTION [bit 13 to bit 11] Reserved bit These bits are reserved bits. Writing has no effect on the operation. Reading is indeterminate. [bit 10] DRQI: Transmission data interrupt request bit It indicates that IN packet has been successfully transferred from the EP0 host, data has been read from the transmission buffer, and the next transmit data can be written into the buffer.
Page 304: Ep0O Status Register (Ep0Os)
CHAPTER 13 USB FUNCTION 13.3.8 EP0O Status Register (EP0OS) The EP0O status register (EP0OS) displays status related to transfer toward out for EndPoint0. EP0O Status Register (EP0OS) Figure 13.3-10 shows the bit configuration of the EP0OS register (EP0OS). Figure 13.3-10 EP0O Status Register (EP0OS) Address 0000E4 Reserved...
Page 305 CHAPTER 13 USB FUNCTION [bit 14] DRQOIE: Received data interruption permission bit It allows an interrupt due to the interrupt factor for the EP0O status register "DRQO" to be generated. DRQOIE Operating mode Interrupt disabled by DRQO factor Interruption permission by DRQO factor [bit 13] SPKIE: Short packet interruption permission bit It allows an interrupt due to the interrupt factor for the EP0O status register "SPK"...
Page 306 CHAPTER 13 USB FUNCTION [bit 8, bit 7] Reserved bit These bits are reserved bits. Writing has no effect on the operation. Reading is indeterminate. [bit 6 to bit 0] SIZE: Packet size display bit When OUT packets have been transferred from EP0, the number of data bytes that has been written into the receive buffer is displayed.
Page 307: Ep1 To Ep5 Status Register (Ep1S To Ep5S)
CHAPTER 13 USB FUNCTION 13.3.9 EP1 to EP5 Status Register (EP1S to EP5S) The EP1 to EP5 status registers (EP1S to EP5S) displays status related to EndPoint1 to EndPoint5. EP1 to EP5 Status Register (EP1S to EP5S) Figure 13.3-11 shows the bit configurations of the EP1 to EP5 status registers (EP1S to EP5S). Figure 13.3-11 EP1 to EP5 Status Register (EP1S to EP5S) Address EP1S 0000E6...
Page 308 CHAPTER 13 USB FUNCTION [bit 15] BFINI: Transmission/receive buffer initialization bit The transmission and reception buffer of the forwarding data is initialized. The BFINI bit is automatically set by setting the RST bit in the UDC control register (UDCC). Consequently, when the reset operation has been performed with the RST bit, clear the RST bit before clearing the BFINI bit.
Page 309 CHAPTER 13 USB FUNCTION [bit 11] BUSY: Busy flag bit It indicates that writing into the transmission/receive buffer or accessing it for read from the HOST is under way. The BUSY bit is set by the automatic operation, and reset. BUSY Operating mode There is no access by HOST.
Page 310 CHAPTER 13 USB FUNCTION [bit 9] SPK: Short packet interrupt request bit It indicates that the number of pieces of transfer data that has been successfully received from the host is less than a maximum number of packets set the PKS in the EP1 to EP5 control register (EP1C to EP5C) (including 0 packet).
Page 311: Ep0 To Ep5 Data Register (Ep0Dt To Ep5Dt)
CHAPTER 13 USB FUNCTION 13.3.10 EP0 to EP5 Data Register (EP0DT to EP5DT) The EP0 to EP5 data registers (EP0DT to EP5DT) are access registers used to read or write into the transmission/receive buffer for transfer data related to EndPoint0 to EndPoint5.
Page 312: Operation Explanation Of Usb Function
CHAPTER 13 USB FUNCTION 13.4 Operation Explanation of USB Function The USB Function conforms to the USB (Universal Serial Bus) communication protocol and supports basic protocol operations (handshake) by hardware. Consequently, only processing communication data can provide the USB communication. Operation of USB Function The USB Function performs two-way packet transfer with a host controller that supports the USB protocol.
Page 313 CHAPTER 13 USB FUNCTION Figure 13.4-1 Example of Connecting for USB Cable Terminal Direction Overview of operaiton USB bus connection Host Device Operation is not started until the host detects detection pull-up on the USB bus. Host Device Data of descripter is returned to the host. Acquiring descriptor information Host...
Page 314 CHAPTER 13 USB FUNCTION Connection detection The device sends a notification to the host PC. The host monitors two signal lines (D + and D-) of the USB bus and recognizes that the device is connected to it by discovering that either signal gets to "H" level. A device must perform processing in the following steps: 1.
Page 315 CHAPTER 13 USB FUNCTION Getting descriptor The device receives a request from the host PC and sends data to the host. In more detail, communications are performed in the following three stages: Figure 13.4-3 Communication Stage → → status stage Setup stage data stage The setup stage ensures that the device receives normal packets from the host PC and identify the command...
Page 316: Each Register Operation When Command Responds
CHAPTER 13 USB FUNCTION 13.4.1 Each Register Operation when Command Responds This section describes basic operations and control of registers and then how to process USB packets (architecture). Firmware tasks triggered via CPU interrupt are processed for each handshake operation. This is equivalent to processing each packet on a per-stage basis.
Page 317 CHAPTER 13 USB FUNCTION Command completion processing The DRQI is set when the status stage toward OUT has been completed. It enters a CPU interrupt process when the DRQO is set, confirms that the number of received data is 0, and clears the interrupt cause DRQO and returns to the interrupted point to prepare for the next setup stage.
Page 318: Suspend Function
CHAPTER 13 USB FUNCTION 13.4.2 Suspend Function A USB device must have a configuration of bus power supply where power consumption is 500µA or less in suspend status. The section covers a USB device from its transmitting to suspend status to its entering STOP mode. Suspend Processing When the USB device core detects suspend status, SUSP of the UDCS register is set to be enabled.
Page 319: Wake-Up Function
CHAPTER 13 USB FUNCTION 13.4.3 Wake-up Function To shift a USB device from suspend status to wake-up status, the USB protocol provides the following two ways: • Remote wake-up from device • Wake-up from host PC The above is explained. Remote Wake-up Figure 13.4-7 Remote Wake-up Operation Suspend state...
Page 320: Dma Transfer Function
CHAPTER 13 USB FUNCTION 13.4.4 DMA Transfer Function It is possible to transfer data between transmission/receive buffer and internal RAM that the USB Function communicates. You can select the following two modes in DMA transfer: one is packet transfer mode where data is transferred based on the number of pieces of transfer set on a per-packet basis and another is data number automatic transfer mode where all data is transferred based on the number of pieces of data specified once.
Page 321 CHAPTER 13 USB FUNCTION IN direction (host PC → device) forwarding Figure 13.4-10 IN Packet Forwarding IN packet IN packet Host PC Device DRQ flag * Device DRQ flag * DATA0 DATA1 CPU clear Host PC CPU clear DMAE DRQIE DER(Enx) DMA sending buffer write DMA sending buffer write...
Page 322 CHAPTER 13 USB FUNCTION Figure 13.4-11 OUT Direction (Host PC → Device) Forwarding OUT packet Last OUT packet Host PC Device OUT DATA1 DATA0 DRQ flag * Device DRQ flag * Automatic clear Host PC Automatic clear DMAE DRQIE DATA0 DATA1 SIZE DER(Enx)
Page 323 CHAPTER 13 USB FUNCTION Figure 13.4-12 IN Direction (Device → Host PC) Forwarding Last data Data Host PC Device DRQ flag * DRQ flag * Device DATA1 Automatic DATA0 Automatic Host PC clear clear DMAE DRQIE DATA0 DATA1 DER(Enx) Write PKS part of Write the rest of DMA sending buffer DMA sending buffer...
Page 324: Null Transfer Function
CHAPTER 13 USB FUNCTION 13.4.5 NULL Transfer Function If data sent from the USB Function is the last packet and a maximum number of packets, it is possible to automatically transfer 0-byte data in the next packet transfer. The NULL transfer function requires that DMAE is enabled and is a function that is only valid for IN transfer.
Page 325: Chapter 14 Usb Mini-Host
CHAPTER 14 USB Mini-HOST This chapter describes the functions and operation of USB Mini-HOST. 14.1 Feature of USB Mini-HOST 14.2 Diversity with USB HOST 14.3 Block Diagram of USB Mini-HOST 14.4 Register of USB Mini-HOST 14.5 Operation of USB Mini-HOST 14.6 Each Token Flow Chart of USB Mini-HOST...
Page 326: Feature Of Usb Mini-Host
CHAPTER 14 USB Mini-HOST 14.1 Feature of USB Mini-HOST USB Mini-HOST provides minimum host operations required and is a function that enables data to be transferred to and from Device without PC intervention. Feature of USB Mini-HOST USB Mini-HOST has the following features. •...
Page 327: Diversity With Usb Host
CHAPTER 14 USB Mini-HOST 14.2 Diversity with USB HOST It indicates differences between the USB host and USB Mini-HOST. Diversity with USB Host HOST Mini-HOST Support Hub Transfer Bulk transfer Control transfer Interrupt transfer Isochronous transfer Transfer speed Low Speed Full Speed PRE packet support SOF packet support...
Page 328: Block Diagram Of Usb Mini-Host
CHAPTER 14 USB Mini-HOST 14.3 Block Diagram of USB Mini-HOST Figure 14.3-1 shows the block diagram of USB Mini-HOST. UART Block Diagram of USB Mini-HOST Figure 14.3-1 Block Diagram of USB Mini-HOST Selector Receive control unit Buffer CPU I/F UDC I/F TXENL Transmit control unit...
Page 329: Register Of Usb Mini-Host
CHAPTER 14 USB Mini-HOST 14.4 Register of USB Mini-HOST In USB Mini-HOST, there are the following ten types of registers: • Host control register 0,1(HCNT0/HCNT1) • Host interruption register (HIRQ) • Host error status register (HERR) • Host state status register (HSTATE) •...
Page 330 CHAPTER 14 USB Mini-HOST • Host state status register ← bit number Address: 0000C4 Reserved ALIVE CLKSEL SOFBUSY SUSP TMODE CSTAT HSTATE → (R/W) (R/W) (R/W) (R/W) Read/Write → Initial value • SOF interruption FRAME comparison register ← bit number Address: 0000C5 FRAMECOMP HFCOMP...
Page 331 CHAPTER 14 USB Mini-HOST • FRAME setting Register ← bit number Address:0000CC FRAME0 HFRAME → (R/W) Read/Write → (00000000 Initial value ← bit number Address:0000CD Reserved FRAME1 HFRAME → (R/W) Read/Write → (000 Initial value • Host token end point register ←...
Page 332: Host Control Register 0,1(Hcnt0/Hcnt1)
CHAPTER 14 USB Mini-HOST 14.4.1 Host Control Register 0,1(HCNT0/HCNT1) Host control registers 0,1(HCNT0/HCNT1) specify the USB operation mode and the settings of an interrupt. Host Control Register 0,1(HCNT0/HCNT1) Figure 14.4-1 Bit Configuration of Host Control Register 0, 1 (HCNT0/HCNT1) Host control register 0 ←...
Page 333 CHAPTER 14 USB Mini-HOST [bit 9] CANCEL: Token cancellation permission This bit sets whether a token is to be cancelled when the token (which is issued in an EOF area) has never been executed and is in waiting status if the SOFIRQ bit in the host interrupt register (HIRQ) is "1".
Page 334 CHAPTER 14 USB Mini-HOST [bit 5] CMPIRE: Completion interrupt request enable It sets whether an interrupt is generated when a token has been completed. Only the host mode is effective. It is not initialized with the RST bit in the UDC control register (UDCC). CMPIRE Operation mode Completion interrupt disabled...
Page 335 CHAPTER 14 USB Mini-HOST [bit 1] URST: USB bus reset It is set to USB bus whether reset is generated. It indicates "1" while the USB bus is being reset and turns "0" when it has been completed. It is forbidden to set it to "1" when the SUSP bit in the host state status register (HSTATE) is "1"...
Page 336: Host Interruption Register (Hirq)
CHAPTER 14 USB Mini-HOST 14.4.2 Host Interruption Register (HIRQ) The host interrupt register (HIRQ) indicates for the interrupt request flag for USB Mini- HOST. It can allow an interrupt to be generated by setting the interrupt enable bit in the host control registers (HCNT0/1) except the TCAN bit.
Page 337 CHAPTER 14 USB Mini-HOST [bit 4] URIRQ: USB bus interrupt request It is shown that reset in USB bus ended. When it becomes "1", it gets back to "0" by writing "0" to it. When you write "1" to it, the current state will be preserved. If the URIRE bit in the host control register 0 (HCNT0) is "1", an interrupt is generated when it is "1".
Page 338 CHAPTER 14 USB Mini-HOST [bit 1] DIRQ: Cutting interrupt request It is shown to have detected cutting the device. When it becomes "1", it gets back to "0" by writing "0" to it. When you write "1" to it, the current state will be preserved. If the DIRE bit in the host control register 0 (HCNT0) is "1", an interrupt is generated when it is "1".
Page 339: Host Error Status Register (Herr)
CHAPTER 14 USB Mini-HOST 14.4.3 Host Error Status Register (HERR) The host error status register (HERR) is a register that indicates whether an error occurs or not when sending or receiving data in host mode. Host Error Status Register (HERR) Figure 14.4-3 Bit Configuration of Host Error Status Register (HERR) Host error status register ←...
Page 340 CHAPTER 14 USB Mini-HOST [bit 13] TOUT: Time-out It indicates whether time-out was generated. If "1" is cleared, write "0" to this bit. The bit is updated after the RST bit of the UDC control register (UDCC) is set to "0". TOUT Operation mode There is no time-out.
Page 341 CHAPTER 14 USB Mini-HOST [bit 9, bit 8] HS: Handshake status It indicates the status of handshake operations between transmission and reception in host mode. It indicates NULL when handshake operation is not performed due to any reasons such as an error and the SOF token is completed.
Page 342: Host State Status Register (Hstate)
CHAPTER 14 USB Mini-HOST 14.4.4 Host State Status Register (HSTATE) The host state status register (HSTATE) is a register that indicates the status of the USB circuit such as connections to devices and transfer mode. Note that the CLKSEL bit is also enabled in the function mode.
Page 343 CHAPTER 14 USB Mini-HOST [bit 3] SOFBUSY:SOF timer operation It indicates whether the SOF timer is operating in host mode. Sending SOF stops when "0" is done in the writing. To update them, you must set the RST bit in the UDC control register (UDCC) to "0". SOFBUSY Operation mode SOF timer is stop.
Page 344 CHAPTER 14 USB Mini-HOST [bit 0] CSTAT: Connected state It is whether the device is connected is shown. The terminal for Mini HOST becomes an object. It is not initialized with the RST bit in the UDC control register (UDCC). CSTAT Operation mode Device cut off...
Page 345: Sof Interruption Frame Comparison Register (Hfcomp)
CHAPTER 14 USB Mini-HOST 14.4.5 SOF Interruption FRAME Comparison Register (HFCOMP) The SOF interrupt FRAME comparison register (HFCOMP) is a register used to set data that is compared with the lower 8 bits of FRAME Number for SOF token. If the lower 8 bits of FRAME Number is compared with the HFCOMP register and a match is detected with the SOFIRE bit in host control register 0 (HCNT0) set to "1", an interrupt will be generated by setting the SOFIRQ bit in the host interrupt register (HIRQ) to "1"...
Page 346: Retry Timer Setting Register (Hrtimer)
CHAPTER 14 USB Mini-HOST 14.4.6 Retry Timer Setting Register (HRTIMER) The retry timer setting register (HRTIMER) is a register used to set a retry time period for a token. Retry Timer Setting Register (HRTIMER) Figure 14.4-6 Bit Configuration of Retry Timer Setting Register (HRTIMER) Retry timer setting register ←...
Page 347: Host Address Register (Hadr)
CHAPTER 14 USB Mini-HOST 14.4.7 Host Address Register (HADR) The host address register (HADR) is a register used for an address field when a token is sent. Host Address Register (HADR) Figure 14.4-7 Bit Configuration of Host address Register (HADR) Host address register ←...
Page 348: Eof Setting Register (Heof)
CHAPTER 14 USB Mini-HOST 14.4.8 EOF Setting Register (HEOF) The EOF setting register (HEOF) is a register that sets a time period for which a token is inhibited before the execution of the SOF token. If the data of the SOF timer turns out to be lower than data in the HEOF register as a result of comparing both, and any of an IN token, OUT token, and SETUP token execution requests is made, it will be run after the SOF token is executed.
Page 349: Frame Setting Register (Hframe)
CHAPTER 14 USB Mini-HOST 14.4.9 FRAME Setting Register (HFRAME) The FRAME setting register (HFRAME) is a register that sets a FRAME Number in handling SOF tokens. When you set the TKNEN bits of the host token endpoint register (HTOKEN) to SOF activation, the SOF timer starts and, afterwards, an SOF is automatically sent out every 1 ms.
Page 350: Host Token Endpoint Register (Htoken)
CHAPTER 14 USB Mini-HOST 14.4.10 Host Token Endpoint Register (HTOKEN) The host token endpoint register (HTOKEN) is a register that sets a toggle, endpoint, and token. Host Token Endpoint Register (HTOKEN) Figure 14.4-10 Bit Configuration of Host Token Endpoint Register (HTOKEN) Host token end point register ←...
Page 351 CHAPTER 14 USB Mini-HOST Table 14.4-3 Token Setting bit6 bit5 bit4 Operation No send out SETUP is sent IN is sent. OUT is sent. SOF is sent. Note: The PRE packet is not supported. When the SOFBUSY bit in the host state status register (HSTATE) is "1", setting bit 6, bit 5, and bit 4 to "1", "0", and "0", respectively, is forbidden.
Page 352: Operation Of Usb Mini-Host
CHAPTER 14 USB Mini-HOST 14.5 Operation of USB Mini-HOST The operation of USB Mini-HOST is explained. Connection of device The software detects that the external USB device was connected. Reset of USB bus USB bus is reset. Token packet Three kinds of tokens can be selected at the host mode. Data packet The data packet is transmitted and received.
Page 353: Connection Of Device
CHAPTER 14 USB Mini-HOST 14.5.1 Connection of Device The method for detecting the connection of the external USB device by software is described. Setting of Mini-HOST Function To make it operate as a host of the USB device, set the HOST bit of the host control register 0 (HCNT0) to "1".
Page 354 CHAPTER 14 USB Mini-HOST Figure 14.5-1 Connecting Detection Timing Example of Speed Device (HCNT0 Bit 0 = "0") LIN device connection Terminal D+ for Mini-HOST Terminal D- for Mini-HOST 2.5µs CSTAT bit of HSTATE Indeterminate TMODE bit of HSTATE CNNIRQ of HIRQ bit "0"...
Page 355: Reset Of Usb Bus
CHAPTER 14 USB Mini-HOST 14.5.2 Reset of USB Bus When you set the URST bit of the host control register 0 (HCNT0) to "1" in the host mode, it sends out SE0 for not less than 10 ms and resets the USB bus. When the USB bus has been reset, it sets back the URST bit of the host control register to "0"...
Page 356: Token Packet
CHAPTER 14 USB Mini-HOST 14.5.3 Token Packet If you execute any of an IN token, OUT token, and SETUP token in the host mode, a token packet is started when you set necessary data in the host token register (HTOKEN) after you set the PKS bit of the EP1 control register (EP1C) or EP2 control register (EP2C) based on the host address register (HADR) and the DIR bit in EP1C.
Page 357 CHAPTER 14 USB Mini-HOST incremented by 1. In this case, the CMPIRQ of the host interrupt register (HIRQ) is also set to "1", and the TKNEN bit of the host token endpoint register (HTOKEN) is cleared to (000) . When the CMPIRE bit of host control register (HCNTO) is "1", an interrupt occurs.
Page 358: Data Packet
CHAPTER 14 USB Mini-HOST 14.5.4 Data Packet If a data packet is transmitted after a token packet has been sent, toggle data will be transmitted based on the TGGL bit of the host token endpoint register (HTOKEN), and the buffer data for endpoint 1 or endpoint 2 according to the DIR bit of the EP1 control register (EP1C), CRC16 data, and EOP is sent.
Page 359: Handshake Packet
CHAPTER 14 USB Mini-HOST 14.5.5 Handshake Packet Transmission/reception partner must be informed of your own status via handshake packet. Handshake Packet The reception side transmits one of ACK, NAK, and STALL when it determines through handshake packet whether it can receive data properly or the endpoint supports it. Then, when the USB circuit receives a handshake packet, the received handshake packet is set to the HS bit of the host error status register (HERR).
Page 360: Retry Function
CHAPTER 14 USB Mini-HOST 14.5.6 Retry Function At the termination of the packet, when NAK or an error such as CRC error occurs, and the RETRY bit of the host control register 1 (HCNT1) is "1", it continues to retry during a time period set in the retry timer register (HRTIMER).
Page 361: Sof Interrupt
CHAPTER 14 USB Mini-HOST 14.5.7 SOF Interrupt Once you have set the SOFIRE bit of the host control register 0 (HCNT0) to "1", it sets the SOFIRQ bit of the host interrupt register (HIRQ) to "1" and will generate an interrupt when starting an SOF with the SOFSTEP bit of the host control register 1 (HCNT1) and the SOF interrupt FRAME comparison register (HFCOMP).
Page 362 CHAPTER 14 USB Mini-HOST If you set the CANCEL bit of host control register 1 (HCNT1) to "0", the token set in the host token endpoint register (HTOKEN) is executed after the SOF is sent. Figure 14.5-7 Example of Token Cancel Operation when CANCEL Bit of HCNT1 is "1". IN TOKEN write EOF area execution...
Page 363: Error Status
CHAPTER 14 USB Mini-HOST 14.5.8 Error Status USB Mini-HOST supports various error information. Error Status Stuffing error If continuous 6 bits happen to be "1", one bit of "0" should be inserted in somewhere in the sequence, but the STUFF bit of the host error status register (HERR) is set to "1" as a stuffing error if continuous 7 bits of "1"...
Page 364: Packet End
CHAPTER 14 USB Mini-HOST 14.5.9 Packet End When one packet terminates in USB Mini-HOST, if the CMPIRE bit of the host control register 0 (HCNT0) is "1", an interrupt is generated to set the CMPIRQ bit of the host interrupt register (HIRQ) to "1". Packet End Timing When one packet terminates, an interrupt is generated in the following timing: When the TKNEN bits of the host token end point register (HTOKEN) are (001...
Page 365: Suspend Resume
CHAPTER 14 USB Mini-HOST 14.5.10 Suspend Resume USB Mini-HOST supports suspend and resume operations. Suspend Operation When writing "1" to the SUSP bit of the host state status register (HSTATE), • USB bus high impedance state • Stop of circuit block where clock is not necessary USB Mini-HOST follows the steps above, and puts the USB circuit in suspend status.
Page 366 CHAPTER 14 USB Mini-HOST Figure 14.5-12 Resume Operation by Device (Full Speed Mode) (2) The simple host pins D+ and D- are detected to be K State. Discovers that Mini-HOST pin D + and Mini-HOST pin D - become K State. Pin D+ for Mini-HOST Pin D-...
Page 367 CHAPTER 14 USB Mini-HOST Figure 14.5-14 Resume Operation by Device Connection (4) The device is detected being connected. Connect Pin D+ for Mini-HOST Pin D- for Mini-HOST RWKIRQ bit of HIRQ (RWKIRE="1") HIRQ bit2 Interrupt (DIRE="1") occurs CSTAT bit of HSTATE 2.5µs or more : Drive by resistances of pull-up and pull-down...
Page 368: Cutting Of Device
CHAPTER 14 USB Mini-HOST 14.5.11 Cutting of Device Once both Mini-HOST pins D + and D- become "L", the disconnection timer starts, and sets the CSTAT bit of the host state status register (HSTATE) to "0" when both pins detect "L" for 2.5 µs or longer. Cutting of Device Regardless of Mini-Host mode and function mode, when both Mini-Host pins D+ and D- detect "L"...
Page 369: Each Token Flow Chart Of Usb Mini-Host
CHAPTER 14 USB Mini-HOST 14.6 Each Token Flow Chart of USB Mini-HOST The flow chart of each token of USB Mini-HOST is as follows. IN, OUT, SETUP Token Figure 14.6-1 Flow Chart at IN, OUT, SETUP Token IN,OUT, SETUP TOKEN HADR change? HADR change IN TOKEN...
Page 370 CHAPTER 14 USB Mini-HOST SOF Token Figure 14.6-2 Flow Chart at SOF Token SOF TOKEN HFRAME change? HFRAME change HEOF change? HEOF change TOKEN execution (Setting TGGL and ENDPT is disregarded.) CMPIRQ of HIRQ=1?
Page 371: Chapter 15 Pwc Timer
CHAPTER 15 PWC TIMER This chapter describes an overview of PWC timer, the configuration and function of register, and the PWC timer operation and precaution. 15.1 Overview of PWC Timer 15.2 Register of PWC Timer 15.3 Movement of PWC Timer 15.4 Precautions when Using PWC Timer...
Page 372: Overview Of Pwc Timer
CHAPTER 15 PWC TIMER 15.1 Overview of PWC Timer The PWC timer is the multi-functional 16-bit up count timer that has the function to measure the pulse width of input signal. PWC: Pulse Width Count (pulse width measurement) Function of PWC Timer Following functions are implemented by hardware of a single channel including a 16-bit up count timer, a register to control input pulse divider and division ratio, a measurement input terminal, and a 16-bit control register:...
Page 373 CHAPTER 15 PWC TIMER Block Diagram of PWC Timer Figure 15.1-1 shows the PWC timer block diagram. Figure 15.1-1 Block Diagram of PWC Timer PWCR read Error detection Internal clock (Machine clock/4) PWCR Reload Data tranmit Clock Overflow 16-bit Up count timer Clock divider Timer clear...
Page 374: Register Of Pwc Timer
CHAPTER 15 PWC TIMER 15.2 Register of PWC Timer Configuration and function of the register used for PWC timer are described. Register List of PWC Timer Figure 15.2-1 shows the PWC timer register list. Figure 15.2-1 Register List of PWC Timer (R/W) PWCSR (R/W)
Page 375: Pwc Control Status Register (Pwcsr)
CHAPTER 15 PWC TIMER 15.2.1 PWC Control Status Register (PWCSR) Configuration and function of PWC control status register (PWCSR) are described. PWC Control Status Register (PWCSR) Figure 15.2-2 shows the bit configuration of PWC control status register (PWCSR). Figure 15.2-2 Bit Configuration of PWC Control Status Register (PWCSR) PWCSR 00005D STRT STOP EDIR EDIE OVIR OVIE...
Page 376 CHAPTER 15 PWC TIMER • Read and write are enabled. However, meanings are different between when writing and reading as shown in Table 15.2-1 and Table 15.2-2. • The value read by read-modify-write instructions is always "11 " regardless of the bit value. •...
Page 377 CHAPTER 15 PWC TIMER [bit 10] OVIE (timer overflow interrupt request permission) Measurement termination interrupt request during the pulse width measurement is controlled as shown in the table below: OVIE Operation mode Overflow interrupt request output disabled (interrupt is not generated even if OVIR is set). [Initial value] Overflow interrupt request output enabled (interrupt is generated when OVIR is set).
Page 378 CHAPTER 15 PWC TIMER [bit 5, bit 4] PIS1, PIS0 (pulse width measurement input terminal selection) The pulse width measurement input terminal is selected. Table 15.2-4 Selection of Pulse Width Measurement Input Terminal PIS1 PIS0 Operation mode (The terminal PWC is selected). [Initial value] Setting disabled Setting disabled Setting disabled (Undefined)
Page 379 CHAPTER 15 PWC TIMER [bit 2 to bit 0] MOD2, MOD1, MOD0 (operation mode/measurement edge selection) Operation mode and width measurement edge are selected. Table 15.2-6 Selection of Operating Mode/measurement Edge of 16-bit Up-count Timer MOD2 MOD1 MOD0 Operation mode/measurement edge selection Timer mode [Initial value] Timer mode (only Reload mode) Pulse width measurement mode between all edges...
Page 380: Pwc Data Buffer Register (Pwcr)
CHAPTER 15 PWC TIMER 15.2.2 PWC Data Buffer Register (PWCR) Configuration and function of PWC data buffer register (PWCR) are described. PWC Data Buffer Register (PWCR) Figure 15.2-3 shows the bit configuration of PWC data buffer register (PWCR). Figure 15.2-3 Bit Configuration of PWC Data Buffer Register (PWCR) PWCR 00005F PWC data buffer register...
Page 381: Pwc Ratio Of Dividing Frequency Control Register (Divr)
CHAPTER 15 PWC TIMER 15.2.3 PWC Ratio of Dividing Frequency Control Register (DIVR) Configuration and function of PWC Ratio of dividing frequency control register (DIVR) are described. PWC Ratio of Dividing Frequency Control Register (DIVR) Figure 15.2-4 shows the bit configuration of a PWC ratio of dividing frequency control register (DIVR). Figure 15.2-4 Bit Configuration of PWC Ratio of Dividing Frequency Control Register (DIVR) DIVR −...
Page 382: Movement Of Pwc Timer
CHAPTER 15 PWC TIMER 15.3 Movement of PWC Timer The movement of the PPG timer is explained. Outline of PWC Timer Operation The PWC timer, a multi-functional timer based on the 16-bit up count timer has built-in measurement input terminal, 8-bit input division, etc. PWC timer has the following two main functions: •...
Page 383: Operation Of Pwm Timer Functions
CHAPTER 15 PWC TIMER 15.3.1 Operation of PWM Timer Functions The up count timer enables the reload and one-shot operations. Operation of PWM Timer Functions Performs the count up at every count clock after starting the timer. An interrupt request may occur when an overflow occurs in the range between 0000 and FFFF The following operation is executed due to the mode when an overflow occurs:...
Page 384: Operation Of Pulse Width Measurement Function
CHAPTER 15 PWC TIMER 15.3.2 Operation of Pulse Width Measurement Function Time cycle between arbiter events of input pulse can be measured by the time. Operation of Pulse Width Measurement Function The pulse width measurement function does not start the count until the set measurement start edge is input after it is started.
Page 385: Count Clock Selection And Operation Mode Selection
CHAPTER 15 PWC TIMER 15.3.3 Count Clock Selection and Operation Mode selection Count clock selection and operation mode selection are described. Count Clock Selection Timer count clock can be selected from three types of internal clock sources by setting the RWCSR bit 7 (CKS1) and bit 6 (CKS0).
Page 386 CHAPTER 15 PWC TIMER Table 15.3-2 Setting Contents of Operation Mode/measurement Mode Content Operating mode MOD2 MOD1 MOD0 Timer Single shot timer Reload timer ↑ or ↓ - ↑ or ↓ Pulse width Single measurement: Buffer invalidity measurement Measurement between all Continuous measurement: Buffer effective edges Measurement at cycle of...
Page 387: Startup And Stop Of Timer/Pulse Width Measurement
CHAPTER 15 PWC TIMER 15.3.4 Startup and Stop of Timer/Pulse Width Measurement Start/restart/stop/forced stop of each operation are performed by using the PWCSR bit 15 and PWCSR bit 14 (STRT and STOP bits). Startup and Stop of Timer/Pulse Width Measurement Functions are separated so that the STRT bit starts and restarts the timer/pulse width measurement and the STOP bit forcibly stops the measurement when "0"...
Page 388 CHAPTER 15 PWC TIMER Pulse width measurement mode In the state of measurement starting edge waiting there is no influence in the operation. During the measurement, the count is stopped and the measurement start edge is again waited. In this case, if the measurement termination edge detection and the restart occur at the same time, the measurement termination flag (EDIR) is set and the result is transferred to PWCR in the continuous measurement mode.
Page 389: Operation Of Timer Mode
CHAPTER 15 PWC TIMER 15.3.5 Operation of Timer Mode The operation of the timer mode is explained. Clearing Timer The 16-bit up count timer is cleared to be 0000 in the following case: • At a reset • In the pulse width measurement mode, when the measurement start edge is detected and the count is started.
Page 390 CHAPTER 15 PWC TIMER Timer Cycle If 0000 is set to the PWCR in the one-shot operation mode and the timer is started, an overflow occurs after 65536 times counted up to stop the count. The time period from the start to the stop is calculated by the following expression: ) •...
Page 391 CHAPTER 15 PWC TIMER Operation Flow of Timer Figure 15.3-4 shows the timer operation flow. Figure 15.3-4 Operation Flow of Timer Count clock selection Operation/ Each Measurement settings mode selection Interrupt flag clear Interrupt enabled Set value to PWCR Start by STRT bit Restart Reload operation mode One-shot operation mode...
Page 392: Operation Of Pulse Width Measurement Mode
CHAPTER 15 PWC TIMER 15.3.6 Operation of Pulse Width Measurement Mode Operation of pulse width measurement mode is described. Single Measurement and Continuous Measurement Pulse width measurement modes include a mode to perform only one-time measurement and a mode to perform continuous measurements.
Page 393 CHAPTER 15 PWC TIMER Measurement Mode and Counter Operation The measurement mode can be selected from six types depending on the place where the input pulse is measured. The cycle measurement mode is also prepared to arbitrarily divide the input pulse for high- precision measurement of higher frequency pulse width.
Page 394 CHAPTER 15 PWC TIMER Table 15.3-6 The Measurement Mode List (2/2) Measurement MOD2 MOD1 MOD0 Measurement mode measured target mode (W: width of a measured pulse) Measurement at Count stop Count start Start Stop cycle of dividing (Example of 4 division) frequency For only dividing ratio selected by division setting register DIVR The input pulse is divided and the cycle is measured.
Page 395 CHAPTER 15 PWC TIMER Range of Count at Pulse Width/cycle Measurable ranges of pulse width/cycle vary depending on the selected combination of division ratios of count clock and input divider. Table 15.3-7 shows the measurement range list of machine clock when the clock frequency (called Φ hereafter) is 24 MHz.
Page 396 CHAPTER 15 PWC TIMER Operation Flow of Pulse Width Measurement Figure 15.3-5 shows the pulse width measurement operation flow. Figure 15.3-5 Operation Flow of Pulse Width Measurement Count clock selection Operation/ Each Measurement settings mode selection Interrupt flag clear Interrupt enabled Restart Start by STRT bit Continuous...
Page 397: Precautions When Using Pwc Timer
CHAPTER 15 PWC TIMER 15.4 Precautions when Using PWC Timer Precautions when using the PWC timer are described. Precautions when Using PWC Timer Notes concerning rewriting register Following bits among PWCSRs are inhibited to be updated during the operation. Always update the bits before starting or after stopping the operation.
Page 398 CHAPTER 15 PWC TIMER Minimum pulse width There are following limitations for pulses that can be input to width measurement input terminals: • Minimum pulse width: 2 divisions of machine clock (0.25µs or more for 16-MHz machine clock) • Minimum input frequency: 4 divisions of machine clock (4 MHz or less for 16-MHz machine clock) When the input pulse width is smaller or the input pulse frequency is higher than the above description, the operation cannot be guaranteed.
Page 399: Chapter 16 16-Bit Reload Timer
CHAPTER 16 16-BIT RELOAD TIMER This chapter describes an overview of 16-bit reload timer, the configuration and functions of register and the 16-bit reload timer operation. 16.1 Overview of 16-bit Reload Timer 16.2 Registers of 16-bit Reload Timer 16.3 Movement of 16-bit Reload Timer...
Page 400: Overview Of 16-Bit Reload Timer
CHAPTER 16 16-BIT RELOAD TIMER 16.1 Overview of 16-bit Reload Timer The 16-bit reload timer provides two functions either one of which can be selected, the internal clock that performs the count down by synchronizing with 3-type internal clocks and the event count mode that performs the count down by detecting the arbiter edge of pulses input to the external terminal.
Page 401: Function Of 16-Bit Reload Timer
CHAPTER 16 16-BIT RELOAD TIMER 16.1.1 Function of 16-bit Reload Timer This section describes overview and Function of 16-bit reload timer. Operation Modes of 16-bit Reload Timer Clock Mode Counter operation 16-bit reload timer operation Reload mode Software trigger operation Internal clock External trigger operation One-shot mode...
Page 402 CHAPTER 16 16-BIT RELOAD TIMER Counter Operation Mode Reload mode → FFFF When an underflow (0000 ) occurs during the count down, the count setting value is reloaded to continue the count operation. Interrupt request that can be generated at the underflow occurrence can be also used as an interval timer.
Page 403: Block Diagram Of 16-Bit Reload Timer
CHAPTER 16 16-BIT RELOAD TIMER 16.1.2 Block Diagram of 16-bit Reload Timer Block Diagram of 16-bit Reload Timer is shown. Block Diagram of 16-bit Reload Timer Figure 16.1-1 Block Diagram of 16-bit Reload Timer Internal data bus TMRLR0 to TMRLR2 16-bit reload register Reload signal TMR0 to TMR2...
Page 404: Registers Of 16-Bit Reload Timer
CHAPTER 16 16-BIT RELOAD TIMER 16.2 Registers of 16-bit Reload Timer Configuration and functions of register used for the 16-bit reload timer are described. Register List of 16-bit Reload Timer Figure 16.2-1 is shown the list of the register of 16-bit reload timer. Figure 16.2-1 List of Register of 16-bit Reload Timer TMCSR0 to TMCSR2 −...
Page 405: Timer Control Status Register 0 To 2 (Tmcsr0 To Tmcsr2)
CHAPTER 16 16-BIT RELOAD TIMER 16.2.1 Timer Control Status Register 0 to 2 (TMCSR0 to TMCSR2) Configuration and functions of timer control status registers 0 to 2 (TMCSR0 to TMCSR2) are described. Timer Control Status Register 0 to 2 (TMCSR0 to TMCSR2) The timer control status registers 0 to 2 (TMCSR0 to TMCSR2) control the operation mode and interrupt of 16-bit reload timer.
Page 406 CHAPTER 16 16-BIT RELOAD TIMER [bit 9 to bit 7] MOD2, MOD1, MOD0 This bit is used to set the operation mode and the I/O terminal functions. The input terminal functions as a trigger at MOD2=0. When the active edge is input to the input terminal and the count operation proceeds, the content of the reload register is loaded to the counter.
Page 407 CHAPTER 16 16-BIT RELOAD TIMER [bit 5] OUTL (setting of output level) This bit is used to set the TOT0 to TOT2 pin output level. OUTL and the output pin level reverses in 0/ OUTL At One-shot mode (RELD=0) At Reload mode (RELD=1) Short-shape wave during counting "H"...
Page 408 CHAPTER 16 16-BIT RELOAD TIMER [bit 1] CNTE (timer counter permission) It is a bit by which the timer counter is permitted. CNTE Function Counter stop [Initial value] Counter permission (startup trigger waiting) [bit 0] TRG (Software trigger) It is Software trigger bit. When 1 is written on the TRG, the software trigger is applied so that the reload register contents of timer is loaded to the counter to start the count operation.
Page 409: 16-Bit Timer Register 0 To 2 (Tmr0 To Tmr2)/ 16-Bit Reload Register 0 To 2 (Tmrlr0 To Tmrlr2)
CHAPTER 16 16-BIT RELOAD TIMER 16.2.2 16-bit Timer Register 0 to 2 (TMR0 to TMR2)/ 16-bit Reload Register 0 to 2 (TMRLR0 to TMRLR2) Configuration and functions of 16-bit timer registers 0 to 2 (TMR0 to TMR2)/16-bit reload registers 0 to 2 (TMRLR0 to TMRLR2) are described. 16-bit Timer Register 0 to 2 (TMR0 to TMR2)/16-bit Reload Register 0 to 2 (TMRLR0 to TMRLR2) Figure 16.2-3 shows the bit configuration of 16-bit timer registers 0 to 2 (TMR0 to TMR2)/16-bit reload...
Page 410 CHAPTER 16 16-BIT RELOAD TIMER 16-bit Reload Register 0 to 2 (TMRLR0 to TMRLR2) Set the initial counter value to the registers TMRLR0 to TMRLR2 in the status the counter operation is inhibited (CNTE = 0 for TMCSR0 to TMCSR2) regardless of the 16-bit reload timer operation. When the counter operation is permitted (CNTE = 1 for TMCSR0 to TMCSR2) and the counter is started, the count down is started from the value written in the registers TMRLR0 to TMCSR2.
Page 411: Movement Of 16-Bit Reload Timer
CHAPTER 16 16-BIT RELOAD TIMER 16.3 Movement of 16-bit Reload Timer The 16-bit reload timer setting and the counter operation status transition are described. Setting of 16-bit Reload Timer Setting of internal clock mode To operate it as an interval timer, the setting shown in Figure 16.3-1 is necessary. Figure 16.3-1 Setting of Internal Clock Mode TMCSR0 −...
Page 412: State Transition Of Counter Operation
CHAPTER 16 16-BIT RELOAD TIMER 16.3.1 State Transition of Counter Operation The state transition of the counter operation is shown. State Transition of Counter Operation Figure 16.3-3 State Transition of Counter Operation Reset STOP state CNTE = 0, WAIT = 1 TIN pin: input disabled TOT pin: general-purpose I/O port 16-bit timer register:...
Page 413: Operation Of Internal Clock Mode (Reload Mode)
CHAPTER 16 16-BIT RELOAD TIMER 16.3.2 Operation of Internal Clock Mode (Reload Mode) It is synchronized with the internal count clock, the 16-bit counter performs the count down, and the counter underflow generates the CPU interrupt request. Also can output toggle waveforms from the timer output pin.
Page 414 CHAPTER 16 16-BIT RELOAD TIMER Figure 16.3-5 Count Operation in the Reload Mode (external Trigger Operation) Count clock −1 −1 −1 −1 Counter Reload Reload Reload Reload 0000 0000 0000 data data data data Data load signal UF bit CNTE bit TIN pin 2T to2.5T* TOT pin...
Page 415: Operation Of Internal Clock Mode (Single Shot Mode)
CHAPTER 16 16-BIT RELOAD TIMER 16.3.3 Operation of Internal Clock Mode (Single Shot Mode) It is synchronized with the internal count clock, the 16-bit counter performs the count down, and the counter underflow generates the CPU interrupt request. Also the TOT pin can output rectangular waveforms indicating that counting is going on.
Page 416 CHAPTER 16 16-BIT RELOAD TIMER Figure 16.3-8 Count Operation in One-shot Mode (external Trigger Operation) Count clock −1 −1 Reload 0000 FFFF Reload 0000 FFFF Counter data data Data load signal UF bit CNTE bit TIN pin 2T to 2.5T* TOT pin Start trigger input wait T: Machine cycle...
Page 417: Event Count Mode
CHAPTER 16 16-BIT RELOAD TIMER 16.3.4 Event Count Mode When the input edge from the TIN pin is counted, the 16-bit counter is counted down and the counter underflow occurs, the CPU interrupt request is generated. In addition, the toggle waveform or the rectangular waveform can be output from the TOT pin. Event Count Mode When the count operation is permitted (CNTE = 1 for TMCSR) and the counter is started (TRG = 1 for TMCSR), the 16-bit reload register (TMRLR) value is loaded to the counter.
Page 418 CHAPTER 16 16-BIT RELOAD TIMER Operation of One-shot mode " → "FFFF When the counter value underflows ("0000 "), the counter stops in the state of "FFFF ". At this moment, if the underflow request flag bit (UF) is set to "1" and the interrupt request output permission bit (INTE) is "1", the interrupt request is generated.
Page 419: Chapter 17 8/16-Bit Ppg Timer
CHAPTER 17 8/16-BIT PPG TIMER This chapter describes an overview of 8/16-bit PPG timer, the configuration and functions of register, and the 8/16-bit PPG timer operation. 17.1 Overview of 8/16-bit PPG Timer 17.2 Registers of 8/16-bit PPG Timer 17.3 Operation of 8/16-bit PPG Timer...
Page 420: Overview Of 8/16-Bit Ppg Timer
CHAPTER 17 8/16-BIT PPG TIMER 17.1 Overview of 8/16-bit PPG Timer The 8/16-bit PPG timer provides the PPG output via the pulse output according to the timer operation with the 8-bit reload timer module. It has the following as a hardware. •...
Page 421: Block Diagram Of 8/16-Bit Ppg Timer
CHAPTER 17 8/16-BIT PPG TIMER 17.1.1 Block Diagram of 8/16-bit PPG Timer Block diagram of ch0/ch2/ch4 and ch1/ch3/ch5 of 8/16-bit PPG timer is shown. Block Diagram of 8/16-bit PPG Timer Figure 17.1-1 shows the block diagram of ch0/ch2/ch4. Figure 17.1-2 shows the block diagram of channels 1/3/5.
Page 422 CHAPTER 17 8/16-BIT PPG TIMER Figure 17.1-2 Block Diagram of 8/16-bit PPG Timer (ch1/ch3/ch5) PPG1/PPG3/PPG5 Peripheral clock 16 division Output enabled PPG1/PPG3/PPG5 Peripheral clock 8 division Peripheral clock 4 division Peripheral clock A/D converter 2 division (only PPG1) Peripheral clock PPG1/PPG3/PPG5 Output latch PEN1...
Page 423: Registers Of 8/16-Bit Ppg Timer
CHAPTER 17 8/16-BIT PPG TIMER 17.2 Registers of 8/16-bit PPG Timer Configuration and functions of register used for the 8/16-bit PPG timer are described. Register List of 8/16-bit PPG Timer Figure 17.2-1 shows the register list of 8/16-bit PPG timer. Figure 17.2-1 Register List of 8/16-bit PPG Timer PPGC0/PPGC2/PPGC4 ch0 : 000046...
Page 424: Ppg0/Ppg2/Ppg4 Operation Mode Control Register (Ppgc0/Ppgc2/Ppgc4)
CHAPTER 17 8/16-BIT PPG TIMER 17.2.1 PPG0/PPG2/PPG4 Operation Mode Control Register (PPGC0/PPGC2/PPGC4) Configuration and functions of PPG0/PPG2/PPG4 operation mode control register (PPGC0/PPGC2/PPGC4) are described. PPG0/2/4 Operation Mode Control Register (PPGC0/PPGC2/PPGC4) The PPG0/PPG2/PPG4 operation mode control register (PPGC0/PPGC2/PPGC4) selects the operation mode of ch0/ch2/ch4, controls the pin output, selects the count clock, and controls the trigger.
Page 425 CHAPTER 17 8/16-BIT PPG TIMER [bit 4] PIE0: ppg Interrupt Enable (interrupt to PPG0/PPG2/PPG4 enabled) PPG0/PPG2/PPG4 interrupt inhibition and permission are controlled. PIE0 Operating State Disables the interrupt Interruption permission • If PUF0 is changed to "1" while this bit is "1", an interrupt request is generated. If this bit is "0", no interrupts are generated.
Page 426: Ppg1/Ppg3/Ppg5 Operation Mode Control Register (Ppgc1/Ppgc3/Ppgc5)
CHAPTER 17 8/16-BIT PPG TIMER 17.2.2 PPG1/PPG3/PPG5 Operation Mode Control Register (PPGC1/PPGC3/PPGC5) Configuration and functions of PPG1/PPG3/PPG5 operation mode control register (PPGC1/PPGC3/PPGC5) are described. PPG1/PPG3/PPG5 Operation Mode Control Register (PPGC1/PPGC3/PPGC5) The PPG1/PPG3/PPG5 operation mode control register (PPGC1/PPGC3/PPGC5) selects the operation mode of ch1/ch3/ch5, controls the terminal output, selects the count clock, and controls the trigger.
Page 427 CHAPTER 17 8/16-BIT PPG TIMER [bit 13] PE10: ppg output Enable10 (PPG1/PPG3/PPG5 output pin enabled) Inhibition and permission of pulse output to the external pulse output pin PPG1/PPG3/PPG5 are controlled. PE10 Operating State General-purpose port pin (pulse output interdiction) PPG1/PPG3/PPG5 pulse output (pulse output permission) •...
Page 428 CHAPTER 17 8/16-BIT PPG TIMER [bit 10, bit 9] MD1, MD0: ppg count Mode (operation mode selection) The operation mode of the PPG timer is selected. Operating mode Byte PPG2 channel independent mode (The case multiplied by 3 is enabled). 8-bit prescaler + 8-bit PPG 1channel.
Page 429: Ppg0 To Ppg5 Output Control Register (Ppg01/Ppg23/Ppg45)
CHAPTER 17 8/16-BIT PPG TIMER 17.2.3 PPG0 to PPG5 Output Control Register (PPG01/PPG23/ PPG45) Configuration and functions of PPG0 to PPG5 output control register (PPG01/PPG23/ PPG45) are described. PPG0 to PPG5 Output Control Register (PPG01/PPG23/PPG45) Figure 17.2-4 shows the bit configuration of the PPG0 to PPG5 output control registers (PPG01/PPG23/ PPG45).
Page 430 CHAPTER 17 8/16-BIT PPG TIMER [bit 4 to bit 2] PCM2 to PCM0:ppg Count Mode (count clock selection) These bits select the down counter operation clock of ch0, ch2, and ch4. PCM2 PCM1 PCM0 Operating mode Peripheral Clock (41.6 ns machine clock 24 MHz time) in surrounding Peripheral Clock /2 (83.3 ns machine clock 24 MHz time) in surrounding Peripheral Clock /4 (167 ns machine clock 24 MHz time) in surrounding Peripheral Clock /8 (333 ns machine clock 24 MHz time) in surrounding...
Page 431: Ppg Reload Registers (Prll0 To Prll5, Prlh0 To Prlh5)
CHAPTER 17 8/16-BIT PPG TIMER 17.2.4 PPG Reload Registers (PRLL0 to PRLL5, PRLH0 to PRLH5) Configuration and functions of PPG reload registers (PRLL0 to PRLL5, PRLH0 to PRLH5) are described. PPG Reload Registers (PRLL0 to PRLL5, PRLH0 to PRLH5) Figure 17.2-5 shows the bit configuration of PPG reload registers (PRLL0 to PRLL5, PRLH0 to PRLH5). Figure 17.2-5 PPG Reload Registers ((PRLL0 to PRLL5, PRLH0 to PRLH5) ch0 : 007900 ch1 : 007902...
Page 432: Operation Of 8/16-Bit Ppg Timer
CHAPTER 17 8/16-BIT PPG TIMER 17.3 Operation of 8/16-bit PPG Timer The 8/16-bit PPG timer has the 6 channels (PPG0, PPG1/PPG2, PPG3/PPG4, PPG5) of 8- bit length PPG unit. Each of them can operate 3-type operations in total, the 8-bit prescaler + 8-bit PPG modes and the 16-bit PPG mode by performing the direct-coupled (PPG0 + PPG1/PPG2 + PPG3/PPG4 + PPG5) operations in addition to the independent mode.
Page 433 CHAPTER 17 8/16-BIT PPG TIMER PPG Output Operation The 8/16-bit PPG timer is started to begin the count when both the bit 7 (PEN0) of PPGC0 register for 0 (ch2/ch4) PPG and the bit 15 (PEN1) of PPGC1 register for 1 (ch3/ch5) PPG are set to "1". After the operation started, when "0"...
Page 434 CHAPTER 17 8/16-BIT PPG TIMER Count Clock Selection The count clock used for 8/16-bit PPG timer operation uses the peripheral clock and the time base counter input to allow 6 types of count clock input selection. The bit4 to bit2 (PCM2 to PCM0) of PPG01/PPG23/PPG45 register selects the ch0 (ch2/ch4) clock and the bit7 to bit5 (PCS2 to PCS0) of PPG01/PPG23/PPG45 register selects the ch1 (ch3/ch5) clock.
Page 435 CHAPTER 17 8/16-BIT PPG TIMER 0=T • (L0+1) 0=T • (L0+1) 1=T • (L0+1) • (L1+1) 1=T • (L0+1) • (H1+1) L0:Value of PRLL of ch0 and value of PRLH of ch1 L1:Value of PRLL of ch1 H1:Value of PRLH of ch1 T: input clock cycle 0: Width of "H"...
Page 436 CHAPTER 17 8/16-BIT PPG TIMER Writing Timing to Reload Register In any modes other than the 16-bit PPG mode, the word transfer instruction is recommended to write data into the reload registers PRLL and PRLH. When the data item is written in the register by using the byte transfer instructions for two times, an unexpected pulse width output may be generated depending on the timing.
Page 437: Chapter 18 Dtp/External Interrupt
CHAPTER 18 DTP/EXTERNAL INTERRUPT This chapter describes an overview of DTP/external interrupt, the configuration and functions of register, and the DTP/external interrupt operation. 18.1 Overview of DTP/External Interrupt 18.2 Register of DTP/External Interrupt 18.3 Operation of DTP/External Interrupt 18.4 Precaution of Using DTP/External Interrupt...
Page 438: Overview Of Dtp/External Interrupt
CHAPTER 18 DTP/EXTERNAL INTERRUPT 18.1 Overview of DTP/External Interrupt The DTP (Data Transfer Peripheral) is located between peripherals existing out of the device and the F MC-16LX CPU. It is the peripheral control section that receives a DMA request or an interrupt request generated by the external peripheral, reports it to the MC-16LX CPU, and starts the µDMAC or the interrupt processing.
Page 439: Register Of Dtp/External Interrupt
CHAPTER 18 DTP/EXTERNAL INTERRUPT 18.2 Register of DTP/External Interrupt This section describes the configuration and functions of registers used for the DTP and external interrupts. Register List of DTP/external Interrupt Figure 18.2-1 shows the register list of the DTP/external interrupts. Figure 18.2-1 Register List of DTP/external Interrupt DTP/Interrupt register Address : 00003C...
Page 440 CHAPTER 18 DTP/EXTERNAL INTERRUPT DTP/Interruption Factor Register (EIRR: External Interrupt Request Register) Figure 18.2-3 shows the bit configuration of DTP/interruption factor register (EIRR). Figure 18.2-3 Bit Configuration of DTP/interruption Factor Register (EIRR) EIRR Initial value 00000000 Address : 00003D (However, the object is different between both of them.) The DTP/interrupt factor register (EIRR) indicates the presence of corresponding external DTP/interrupt request when reading and clears the flip-flop contents

Fujitsu F2MC-16LX Hardware Manual

Chapter 1 Overview

Chapter 2 Cpu

Chapter 3 Interrupt

Chapter 4 Reset

Chapter 5 Clock

Chapter 6 Low-Power Consumption Mode

Chapter 7 Mode Setting

Chapter 8 I/O Port

Chapter 9 Timebase Timer

Chapter 10 Watchdog Timer

Chapter 11 Watch Timer

Chapter 12 16-Bit I/O Timer

Chapter 13 Usb Function

CHAPTER 14 USB Mini-HOST

Chapter 15 Pwc Timer

Chapter 16 16-Bit Reload Timer

Chapter 17 8/16-Bit Ppg Timer

Chapter 18 Dtp/External Interrupt

Chapter 19 8/10-Bit A/D Converter

Chapter 20 Extended I/O Serial Interface

Chapter 21 Uart

Chapter 22 I 2 C Interface

Chapter 23 Rom Mirror Function Selection Module

Chapter 24 Address Match Detection Function

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Summary of Contents for Fujitsu F2MC-16LX