External Memory Access Control Signal - Fujitsu F2MC-16LX Hardware Manual

7.5.1

External Memory Access Control Signal

The access to the external memory is performed at 3 cycles unless the ready function is
not used.
External Memory Access Control Signal
Figure 7.5-1 to Figure 7.5-4 show the timing charts of the external access in each mode. The 8-bit bus
width access in the external data bus 16-bit mode reads or writes the 8-bit width peripheral chip when you
connect to the external bus by mixing the 8-bit width peripheral chip and the 16-bit width peripheral chip.
Be sure to connect the 8-bit width peripheral chip to the lower 8-bit of data because the 8-bit bus width
access is executed by the lower 8-bit of the data bus. Whether performing the 16-bit bus width access or the
8-bit bus width access in the external data bus 16-bit mode is determined by the specification of the HMBS/
LMBS bit of EPCR. Furthermore, in the multiplex mode, any actual bus operation may not be performed
by executing only the address output and the assert output of ALE and not asserting RD/WRL/WRH.
Note:
Be sure not to execute the access to the peripheral chip only by using the ALE signal.
External data bus 8-bit mode (non-multiplex mode)
Figure 7.5-1 Timing Chart of External Memory Access (External Data Bus 8-bit/non-multiplex Mode)
P57/CLK
P53/WRH
P52/WRL
P51/RD
P50/ALE
A23 to A16
A15 to A08
A07 to A00
D15 to D08/
AD15 to AD08
D07 to D00/
AD07 to AD00
Read
(Port data)
Read address
Read address
Read address
(Port data)
Read data
CHAPTER 7 MODE SETTING
Write
Write address
Write address
Write address
Write data
Read
Read address
Read address
Read address
189