Table of Contents
Advertisement
CHAPTER 5 CLOCK
5.3 Clock Select Register (CKSCR)
5.3
Clock Select Register (CKSCR)
The clock select register (CKSCR) switches the clock mode between the main, sub, and
PLL clocks, and selects the oscillation stabilization wait time and the PLL clock
frequency multiplier.
■ Configuration of Clock Select Register (CKSCR)
Figure 5.3-1 shows the clock selection register (CKSCR) configuration. Table 5.3-1 summarizes the
functions of the clock selection register bits.
bit15 bit14 bit13 bit12 bit11 bit10 bit 9
Address
0000A1
Reserved
H
-
R/W
: Readable/Writable
: Read only
R
Initial value
128
Figure 5.3-1 Configuration of Clock Select Register (CKSCR)
MCM WS1 WS0
Reserved
R
R/W R/W
-
FUJITSU MICROELECTRONICS LIMITED
bit 8 bit 7
MCS
CS1
CS0
R/W R/W R/W
Multiplication factor selection bit
CS1 CS0
Each value in parentheses ( ) represents the period
at 6 MHz .
0
0
1×HCLK ( 6MHz)
0
1
2×HCLK (12MHz)
1
0
4×HCLK (24MHz)
1
1
Disable to setting
Machine clock selection bit
MCS
0
PLL clock selection
1
Main clock selection
Oscillation stabilization wait time selection bit
WS1 WS0
Each value in parentheses ( ) represents the period
at 6 MHz .
0
0
0
1
13
2
/HCLK ( Approx. 1.36 ms )
15
1
0
2
/HCLK ( Approx. 5.46 ms )
17
1
1
2
/HCLK ( Approx. 21.84 ms )*
17
*:2
/HCLK (approx. 21.85 ms) at power-on reset
Machine clock display bit
MCM
0
During operating at PLL clock
1
During operating at Main clock
Reserved bit
Reserved
Be sure to set this bit to "1".
MB90335 Series
bit 0
Initial value
11111100
(LPMCR)
CM44-10137-6E
B
Advertisement
Table of Contents
