Notes On Using Timebase Timer - Fujitsu F2MC-16LX Hardware Manual

9.6

Notes on Using Timebase Timer

This section explains notes on using the timebase timer, including the effects of
clearing an interrupt request or clearing the timebase timer on peripheral functions.
I Notes on using timebase timer
❍ Clearing an interrupt request
Clearing the interrupt request flag bit (TBOF) of the timebase timer control register (TBTC) must
be implemented in the state where the timebase timer interrupt is masked by the interrupt
request permit bit (TBIE) or by the interrupt level mask register (ILM) setting of the processor
status (PS).
❍ Effect of clearing the timebase timer
Clearing the timebase timer counter affects the following:
• Operations where the interval timer function (interval interrupt) is used by the timebase timer
• Operations using the watchdog timer
❍ Use of the timer for the oscillation stabilization wait time
When power is turned on, the oscillation clock is stopped in the main stop mode. In such a case,
after the oscillator starts operating, the oscillation stabilization wait time of the clock must be
provided by using as a timing reference the operation clock supplied by the timebase timer. An
appropriate oscillation stabilization wait time must be selected depending on the type of
oscillator (resonator) connected to the high-speed oscillation pin. See Section 5.5 "Oscillation
Stabilization Wait Time", for details.
❍ Caution on using peripheral functions whose operation clock is supplied from the
timebase timer
In a mode where the main clock stops, the counter is cleared and the timebase timer stops
operating. Furthermore, because the clock supplied by the timebase timer is reset to the initial
state and is supplied again when the timebase timer counter is cleared, the period of "H" level
may become shorter or the period of "L" level may become longer by a maximum of a 1/2 cycle.
Although the clock for the watchdog timer is also supplied from the initial state, the watchdog
timer operates at normal cycles because the watchdog time counter is cleared at the same time.
CHAPTER 9 TIMEBASE TIMER
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