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MB90335 Series
11.3.9
EP1 to EP5 Status Register (EP1S to EP5S)
The EP1 to EP5 status registers (EP1S to EP5S) displays status related to EndPoint1 to
EndPoint5.
■ EP1 to EP5 Status Register (EP1S to EP5S)
Figure 11.3-11 shows the bit configurations of the EP1 to EP5 status registers (EP1S to EP5S).
Address
bit
7
EP1S 0000E6
H
X
X
R
7
Address
bit
Reserved
EP2S 0000E8
H
0
EP3S 0000EA
H
EP4S 0000EC
0
H
EP5S 0000EE
H
-
Address
bit
15
EP1S 0000E7
BFINI
H
1
1
R/W
Address
bit
15
EP2S 0000E9
BFINI
H
EP3S 0000EB
H
1
EP4S 0000ED
H
1
EP5S 0000EF
H
R/W
R/W : Readable/Writable
R :
Read Only
The function of each bit in the EP1 to EP5 status register (EP1S to EP5S) is described in the following.
CM44-10137-6E
Figure 11.3-11 EP1 to EP5 Status Register (EP1S to EP5S)
6
5
X
X
X
X
R
R
6
5
X
X
X
X
R
R
14
13
DRQIE
SPKIE
0
0
Irrelevance Irrelevance
R/W
R/W
14
13
DRQIE
SPKIE
0
0
Irrelevance Irrelevance
R/W
R/W
FUJITSU MICROELECTRONICS LIMITED
4
3
SIZE
X
X
X
X
R
R
4
3
SIZE
X
X
X
X
R
R
12
11
10
Reserved
BUSY
DRQ
-
0
-
Irrelevance
-
R
R/W
12
11
10
Reserved
BUSY
DRQ
-
0
-
Irrelevance
-
R
R/W
CHAPTER 11 USB FUNCTION
11.3 Registers of USB Function
2
1
0
X
X
X
X
X
X
R
R
R
2
1
0
X
X
X
X
X
X
R
R
R
9
8
SPK
SIZE
0
0
X
0
0
X
R/W
R
9
8
SPK
Reserved
0
0
0
0
0
0
R/W
-
←
Initial value
←
BFINI Reset
←
Access
←
Initial value
←
BFINI Reset
←
Access
←
Initial value
←
BFINI Reset
←
Access
←
Initial value
←
BFINI Reset
←
Access
219
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