Block Diagram Of Low-Power Consumption Control Circuit - Fujitsu MB90335 Series Hardware Manual

MB90335 Series
6.2

Block Diagram of Low-power Consumption Control Circuit

The low-power consumption control circuit is composed of the following seven blocks.
• CPU intermittent operation selector
• Standby controller circuit
• CPU clock controller circuit
• Peripheral clock controller circuit
• Pin high-impedance controller circuit
• Internal reset generator circuit
• Low-power consumption mode control register (LPMCR)
■ Block Diagram of Low-power Consumption Control Circuit
Figure 6.2-1 shows the block diagram of the low-power consumption control circuit.
Figure 6.2-1 Block Diagram of Low-power Consumption Control Circuit
RST
Reset (Cancellation)
Interrupt (Cancellation)
Clock
generation
unit
Pin
X0
X1
Pin
CM44-10137-6E
Low power consumption mode control register (LPMCR)
STP SLP SPL RST TMD
Pin
2
Operation
clock
selector
PLL frequency
MCM
RESERVED
multiplication circuit
Clock selection register (CKSCR)
2
-division
Main
Oscillation clock
clock
(HCLK)
System clock
generation circuit
FUJITSU MICROELECTRONICS LIMITED
CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.2 Block Diagram of Low-power Consumption Control Circuit
CG1 CG0
Reserved
Pin high
impedance
control circuit
Internal reset
generation
circuit
CPU intermittent
operation sector
CPU clock
control circuit
Standby
control circuit
Oscillation stable
wait cancellation
Main clock oscillation stabilization wait cancellation
Machine
clock
2
2
WS1 WS0 MCS CS1 CS0
RESERVED
512 4 2 2
-division -division -division -division
Time-base timer
Pin high
impedance
control
Internal reset
Intermittent cycle
selection
CPU clock
Stop, Sleep signal
Stop signal
Peripheral
clock
control circuit
Oscillation
stable wait
time
selector
2 2 2 4
-division -division -division -division
to Watchdog timer
139