Stop Mode - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.5.4

Stop Mode

The stop mode stops source oscillation and stops all functions, thereby enabling
retention of data with the lowest consumption of power.
I Change to stop mode
Write "1" in the stop mode bit (STP) of the low-power consumption mode control register
(LPMCR) to change the mode to the stop mode.
❍ Data hold function
This function in the stop mode holds data of the internal RAM and dedicated registers such as
an accumulator.
❍ Hold function
In the stop mode, the external bus hold function is stopped and hold requests cannot be
accepted even if they are input. If a hold request is input during a change to the stop mode, the
level of the HAK signal may not change to "L" while the bus is set to the high-impedance state.
❍ Operation during interrupt request
The stop mode is not set if an interrupt request is issued while "1" is set in the STP bit of the
LPMCR register.
❍ Pin state setting
Pin state specification bit (SPL) of the LPMCR register can specify whether to maintain the state
of an external pin in the stop mode in the previous state or in the high-impedance state.
I Canceling the stop mode
The low-power consumption control circuit releases the stop mode when a reset is input or an
interrupt occurs. Because the oscillation clock (HCLK) and sub-clock (SCLK) are halted, the
stop mode is released after the oscillation stabilization wait interval of the main clock or sub-
clock.
❍ Reset by a reset
When the stop mode is canceled by a reset factor, the stop mode is canceled first and the reset
state standing by for stable oscillation is set. The sequence for resetting is executed after the
end of the oscillation stabilization wait time.
❍ Reset by interrupt
The stop mode is canceled by the low-power control circuit if an interrupt request whose
interrupt level is higher than 7 (other than IL2, IL1, and IL0-"111
register (ICR)) is generated in a peripheral circuit, etc., in the stop mode. After the stop mode is
canceled, interrupts are processed with the same method as for ordinary interrupt processing,
following the elapse of the oscillation stabilization wait time of the main clock specified by the
selection bits (WS1, WS0) for the oscillation stabilization wait time of the clock selection register
(CKSCR). If the interrupts are accepted by setting the I-flag of the condition code register
(CCR), interrupt level mask register (ILM) or the interrupt control register (ICR), the CPU
executes interrupts. If an interrupt cannot be accepted, the CPU continues processing beginning
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