Operation Of Delayed Interrupt Generation Module - Fujitsu F2MC-16LX Hardware Manual

3.12.1

Operation of Delayed Interrupt Generation Module

When the CPU writes "1" to the appropriate bit of the DIRR by software, the request
latch in the delay interrupt generation module is set, resulting in generation of the
interrupt request to the interrupt controller.
Operation of Delayed Interrupt Generation Module
When the CPU writes "1" to the appropriate bit of the DIRR by software, the request latch in the delay
interrupt generation module is set, resulting in generation of the interrupt request to the interrupt controller.
If all the other interrupt requests have a lower priority than that of this one, or no other requests have been
generated, the interrupt controller generates the interrupt to F
compares the ILM bit in the internal CCR register with interrupt request, if the request level is higher than
the ILM bit, a hardware interrupt processing microprogram is activated as soon as the current execution
instruction is completed. As a result, the interrupt routine is executed for this interrupt. The interrupt cause
is cleared by writing 0 to the appropriate bit of the DIRR in the interrupt handling routine. This also causes
task switching.
Figure 3.12-3 shows the above operation flow.
Figure 3.12-3 Operation of Delayed Interrupt Generation Module
Delayed interrupt
generation module
DIRR
Notes on Use of Delay Interruption Generation Module (Delay Interruption Request
Latch)
This latch is set by writing "1" to the appropriate bit of the DIRR, and cleared by writing "0" to this bit.
Note that for this reason, the interrupt handling may be reactivated immediately when control returns from
the interrupt cause handling, unless the software has been designed to clear the cause in the interrupt
handling routine.
Interrupt controller
Other
request
ICR
YY
ICR
XX
2
MC-16LX CPU. When F
2
F MC-16LX
ICR
XX
CMP
ICR
XX
NTA
CHAPTER 3 INTERRUPT
2
MC-16LX CPU
bus
CMP
111