Watchdog Timer Configuration - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 10 WATCHDOG TIMER

10.3 Watchdog Timer Configuration

The watchdog timer is composed of the following five blocks:
• Count clock selector
• Watchdog counter (2-bit counter)
• Watchdog reset generation circuit
• Counter clear control circuit
• Watchdog timer control register (WDTC)
I Block diagram of watchdog timer
Figure 10.3-1 "Block diagram of watchdog time" is a block diagram of the watchdog timer.
Watch mode start
Timebase timer mode start
Sleep mode start
Hold state start
Stop mode start
HCLK frequency
divided by 2
HCLK: Oscillation clock
SCLK: Sub-clock
❍ Count clock selector
This circuit selects the count clock of the watchdog time from among four types of timebase
timer output and four types of watch timer output. This selection determines the time for
generating a watchdog reset.
❍ Watchdog counter (2-bit counter)
This is a 2-bit up-counter that uses timebase timer output as the count clock.
❍ Watchdog reset generation circuit
This circuit generates a reset signal for an overflow of the watchdog counter.
❍ Counter clear circuit
This circuit controls the clearing of the watchdog counter and the start and stop of the counter.
208
Figure 10.3-1 Block diagram of watchdog timer
Watchdog timer control register (WDTC)
PONR Reserved WRST ERST SRST WTE WT1 WT0
2
Watchdog timer
Count
Counter clear
clock
control circuit
selector
4
Clear
(Timebase timer counter)
× 2 × 2 × 2 × 2 × 2
1 2 8 9
SCLK × 2 × 2 × 2 × 2 × 2
1 2 8 9
WDCS bit in watch timer control register (WTC)
SCM bit in clock selection register (CKSCR)
CLR
and start
CLR
Over-
Watchdog
flow
2-bit
reset
counter generation
circuit
CLR
4
× 2 × 2 × 2 × 2 × 2 × 2 × 2
10 11 12 13 14 15 16
× 2 × 2 × 2 × 2 × 2 × 2 × 2
10 11 12 13 14 15 16
To internal reset
generation circuit
× 2
17 18
× 2
17 18