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CHAPTER 3 CPU
3.8.7
Pin State in Standby Mode, at Reset
The state of input/output pins in the standby mode and at reset is shown in each access
mode.
I State of Input/Output Pins (Single-chip Mode)
Table 3.8-6 State of Input/Output Pins (Single-chip Mode)
Pin Name
P17 to P10
P27 to P20
P37 to P35, P33 to P30
P44 to P40
P57 to P50
*1:Indicates that either the output pins output their state as it is immediately before entering each standby mode or the input
pins are input-disabled. Output of the output state as it is means that when the resource with an output is in operation,
the state of pins is output according to the state of the resource and, when the state of output pins is output, it is
held.Input disabled means that no pin value can be accepted internally because the internal circuit is off while the
operation of the input gates of pins is enabled.
*2:Input cut off means that the operation of the input gates of pins is disabled; output Hi-Z means that the driving of pin
driving transistors is disabled to place the pins in a high impedance state.
Note:
To set that pin to high impedance which serves either for a peripheral resource or as a port in
stop mode, watch mode, or timebase timer mode, disable the output of the peripheral
resource, then set the STP bit to "1" or set the TMD bit to "0".Listed below are applicable
ports.
This applies to the following pins: P14/PPG0, P15/PPG1, P16/PPG2, P17/PPG3, P21/TOT0,
P23/TOT1
146
At stop/clock/timebase timer
At sleep
SPL=0
Input cut off/
Immediately-
immediately-
preceding state
preceding state
*1
held
*1
held
SPL=1
Input cut off/
Input disabled/output
*2
Hi-Z
output Hi-Z
At a reset
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