Input Capture Data Registers (Ipcp0 To Ipcp3) - Fujitsu MB90895 Series Hardware Manual

7.3.4

Input capture data registers (IPCP0 to IPCP3)

The input capture data registers 0 to 3 (IPCP0 to IPCP3) store the counter value of the
16-bit free-run timer read in the timing with the edge detection by the input capture.The
counter value of the 16-bit free-run timer is stored in the input capture data registers
(IPCP0 to IPCP3) corresponding to the input pins (IN0 to IN3) to which an external signal
is input.
I Input capture data registers (IPCP0 to IPCP3)
Input capture data
register (IPCP) : upper
Input capture data
register (IPCP) :lower
R : Read only
X : Undefined
I Operation of Input Capture Data Registers 0 to 3 (IPCP0 to IPCP3)
• At the same time that the edges of signals input from the input pins (IN0 to IN3) of the 16-bit input/
output timer are detected, the counter value of the 16-bit free-run timer is stored in the input capture data
registers 0 to 3 (IPCP0 to IPCP3) corresponding to the input pins (INO to IN3).
Note: Always use a word instruction (MOVW) to read the input capture data registers 0 to 3 (IPCP0
to IPCP3).
Figure 7.3-5 Input capture data registers (IPCP0 to IPCP3)
bit15 bit14 bit13 bit12 bit11 bit10 bit9
CP15 CP14
R R
bit7 bit6
CP7 CP6
R R
CP13 CP12 CP11 CP10
R R R R
bit5 bit4 bit3 bit2
CP5 CP4 CP3 CP2
R R R R
CHAPTER 7 16-bit I/O timer
bit8
Reset value
CP9 CP8
XXXXXXXX
R R
bit1 bit0
Reset value
CP1 CP0
XXXXXXXX
R R
B
B
235