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MB90335 Series
Register of μDMAC
3.8.2
μDMAC has four registers: DCSR, DSR, DSSR, and DER. The DMA descriptor used to
set up DMA transfer is described in "3.8.3 DMA Descriptor Window Register (DDWR)".
■ μDMAC Register List
DMA descriptor channel specification register (DCSR)
bit
00009B
H
R/W
DMA status register (DSRH/DSRL)
bit
00009D
DTE15 DTE14 DTE13 DTE12 DTE11 DTE10
H
R/W
bit
00009C
DTE7
H
R/W
DMA stop status register (DSSR)
bit
0000A4
H
STP15 STP14 STP13 STP12 STP11 STP10 STP9
R/W
bit
0000A4
STP7
H
R/W
(When STP bit of DCSR is "0" and "1", DSSR uses STP8 to STP15 and STP0 to STP7 respectively.)
DMA enable register (DERH/DERL)
bit
EN15
0000AD
H
R/W
bit
0000AC
EN7
H
R/W
R/W: Readable/Writable
CM44-10137-6E
Figure 3.8-1 μDMA Register List
15
14
13
12
STP
Reserved Reserved Reserved
R/W
R/W
R/W
15
14
13
12
R/W
R/W
R/W
7
6
5
DTE5
DTE4
R/W
R/W
R/W
7
6
5
R/W
R/W
R/W
7
6
5
STP6
STP5 STP4
R/W
R/W
R/W
15
14
13
12
EN12
EN14
EN13
R/W
R/W
R/W
7
6
5
4
EN6
EN5
EN4
R/W
R/W
R/W
FUJITSU MICROELECTRONICS LIMITED
11
10
9
DCSR3 DCSR2 DCSR1DCSR0
R/W
R/W
R/W
11
10
9
R/W
R/W
R/W
4
3
2
1
DTE3
DTE2
DTE1
R/W
R/W
R/W
4
3
2
1
R/W
R/W
R/W
4
3
2
STP1
STP2
R/W
R/W
R/W
11
10
9
EN11
EN9
EN10
R/W
R/W
R/W
3
2
1
EN3
EN2
EN1
R/W
R/W
R/W
CHAPTER 3 INTERRUPT
3.8 Interruption by μDMAC
8
DCSR
R/W
Initial value
00000000
8
DTE8
DSRH
R/W
Initial value
00000000
0
DTE0
DSRL
R/W
Initial value
00000000
0
STP8
DSSR
R/W
Initial value
00000000
1
0
STP0
DSSR
R/W
Initial value
00000000
8
DERH
EN8
R/W
Initial value
00000000
0
DERL
EN0
00000000
R/W
Initial value
B
B
B
B
B
B
B
87
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