External Memory Access (External Bus Pin Control Circuit) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 6 MEMORY ACCESS MODES
6.2

External Memory Access (External Bus Pin Control Circuit)

The external bus pin control circuit controls external bus pins used to expand the
address/data buses of the CPU outside.
■ External Memory Access (External Bus Pin Control Circuit)
To access memory/peripheral circuits installed outside the device, the F
following address/data/control signals:
• CLK (P37):
• RDY (P36):
• WRH (P33): Write signal for high-order eight bits of the data bus
• WRL (P32): Write signal for low-order eight bits of the data bus
• RD (P31):
• ALE (P30):
■ Block Diagram of External Memory Access (External Bus Pin Control Circuit)
Figure 6.2-1 shows a block diagram of external memory access (external bus pin control circuit).
Figure 6.2-1 Block Diagram of External Memory Access (External Bus Pin Control Circuit)
P0 direction
RB
Data control
Address control
Access
Access control
control
120
Machine cycle clock (KBP) output pin
External ready input pin
Read signal
Address latch enable signal
P1
P0
P0 data
P3
P2
2
MC-16LX supplies the
P3
P0