Timebase Timer Configuration - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 9 TIMEBASE TIMER
9.2

Timebase Timer Configuration

The timebase timer is composed of the following four blocks:
• Timebase timer counter
• Counter clear circuit
• Interval timer selector
• Timebase timer control register (TBTC)
I Block diagram of timebase timer
Figure 9.2-1 "Block diagram of timebase time" is a block diagram of the timebase timer.
Timebase timer counter
HCLK frequency
× 2
divided by 2
Power-on reset
Stop mode start
CKSCR : MCS = 1→ 0
CKSCR : SCS = 0 → 1
Timebase timer control register (TBTC)
Timebase timer interrupt signal
- : Not used
OF : Overflow
HCLK : Oscillation clock
*1 : Switching the machine clock from the main clock or the sub-clock to the PLL clock
*2 : Switching the machine clock from the sub-clock to the main clock
❍ Timebase timer counter
This is an 18-bit up-counter that uses the oscillation clock (HCLK) frequency divided by 2 as the
count clock.
❍ Counter clear circuit
This circuit clears the counter at the time of writing of "0" to the timebase timer initializing bit
(TBR) in the timebase timer control register (TBTC), a power-on reset, a transition to the main
stop mode, a transition to the PLL stop mode, switching from the main clock mode to the PLL
clock mode, switching from sub-clock mode to the PLL clock mode, and switching from the sub-
clock mode to main clock mode.
192
Figure 9.2-1 Block diagram of timebase timer
To PPG timer
× 2 × 2 × 2 × 2
1 2 3 8
Counter
clear circuit
(*1)
(*2)
RESV
× 2 × 2 × 2 × 2 × 2 × 2
9 10 11 12 13 14
OF
OF
OF
Interval timer
selector
TBOF
set
TBOF clear
TBIE TBOF TBR
To watchdog
timer
× 2 × 2 × 2
15 16 17 18
OF
To selector of oscillation
stabilization wait time
in clock control section
TBC1 TBC0