Table 6.3.2B Cs Bit Settings - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

6.3 Registers and register details
[Bit 10] MCS
This bit selects either the main clock or the PLL clock as the machine clock. When a "0" is written to
this bit, the PLL clock is selected; when a "1" is written to this bit, the main clock is selected. If a "0" is
written to this bit while it is "1", the oscillation stabilization waiting period for the PLL clock is
generated; therefore, the timebase timer is automatically cleared. Note that the PLL clock oscillation
stabilization waiting period is fixed at 2
is used for the operation clock when the main clock is selected. (When the source oscillation is 4 MHz,
the operation clock is 2 MHz.)
This bit is initialized to "1" by a reset due to power-on, hardware standby, or the watchdog timer.
[Bits 9, 8] CS1, CS0
These bits select the PLL clock multiplier. These bits are not initialized by a reset initiated by an
external pin or the RST bit. These bits are initialized to "00" by a reset due to power-on, hardware
standby, and the watchdog timer.
Writing to these bits is suppressed when the MCS bit is "0". Set the MCS bit to "1" (main clock mode)
first and then overwrite the CS bits.
These bits can be read and written.
CS1
0
0
1
1
66 Chapter 6: Low Power Control Circuit
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Table 6.3.2b CS Bit Settings

CS0 Machine clock (source oscillation at 4 MHz)
0 4 MHz (operation frequency = OSC oscillation frequency)
1 8 MHz (operation frequency = OSC oscillation frequency × 2)
0 12 MHz (operation frequency = OSC oscillation frequency × 3)
1 12 MHz (operation frequency = OSC (3 MHz) × 4)
main clock cycles. In addition, the main clock divided by two
MB90580 Series