Reset Operation - Fujitsu F2MC-16LX Hardware Manual

4.4

Reset Operation

Once the reset is released, the object from which to read the mode data and reset
vector is selected by setting the mode pin, before the mode fetch is performed. This
fetch determines the CPU operation mode and the execution activation address
succeeding the reset operation. At power on or when recovering from stop mode via a
reset, the mode fetch is performed after the oscillation stabilization delay time elapses.
Overview of Reset Operation
Figure 4.4-1 shows the reset operation flow.
During reset
Mode fetch
(Reset operation)
Normal operation
(RUN state)
Mode Pin
The mode pins (MD2 to MD0) specify the way to fetch the reset vector and mode data. This fetch is
performed according to the reset sequence. See "Section 7.2 Mode Pins (MD2 to MD0)" for details of the
mode pins.
Figure 4.4-1 Reset Operation Flow
Power on reset
Stop mode
Sub clock mode
Oscillation stabilizing wait
reset state
Fetch Mode data
Fetch Reset vector
Capture the instruction code
from the address specified
by reset vector and execute
the instruction
External reset
Software reset
Watchdog timer reset
Pin state and function change
of external bus mode relation
CHAPTER 4 RESET
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