Bus Control Signal Selection Register (Ecsr) - Fujitsu F2MC-16LX Hardware Manual

6.2.4

Bus Control Signal Selection Register (ECSR)

This register sets a control function of bus operation in an external bus mode. This
register cannot be accessed when the device is in the single-chip mode. In this mode,
all pins function as I/O port pins regardless of the value of this register. All bits of this
register are dedicated to writing. For reading, all bits are set to "1".
■ Bus Control Signal Selection Register (ECSR)
Figure 6.2-5 Configuration of the Bus Control Signal Selection Register
Control signal
selection register
Address:0000A7
Read/write
Initial value
[bit15] CKE
The CKE bit controls output of the external clock (CLK) as listed in Table 6.2-5.
Table 6.2-5 Function of CKE (External Clock (CLK) Output Control Bit)
CKE
0
1
[bit14] RYE
The RYE bit controls input of the external ready (RDY) as listed in Table 6.2-6.
Table 6.2-6 Function of RYE (External Ready (RDY) Input Control Bit)
RYE
0
1
[bit13] HDE
The HDE bit enables input/output of hold-related pins. The HDE bit controls hold request
input (HRQ) and hold acknowledge output (HAK) as listed in Table 6.2-7.
6.2 External Memory Access (External Bus Pin Control Circuit)
15 14 13
bit
CKE RYE HDE
H
(W) (W) (W)
(0) (0) (0)
I/O port (P37) operation (Prohibits clock output.)[Initial value]
Enables clock signal (CLK) output.
I/O port (P36) operation (Prohibits external RDY input.)[Initial value]
Enables external ready (RDY) input.
12 11 10 9
IOBS HMBS WRE LMBS
(W) (W) (W) (W)
(0) (0) (0) (0)
Function
Function
8
ECSR
(-)
(-)
125