Interrupts By Extended Intelligent I/O Service (Ei 2 Os) - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 3 INTERRUPT
3.6 Interrupts by Extended Intelligent I/O Service (EI
The extended intelligent I/O service (EI
the peripheral function (I/O) and memory. A hardware interrupt is generated at the end
of the data transfer.
Extended Intelligent I/O Service (EI
The extended intelligent I/O service is a kind of hardware interrupts. EI
transfer between the peripheral function (I/O) and memory. EI
peripheral function (I/O), previously executed by the interrupt handling program, like direct memory access
(DMA), at the end of transfer, and sets the end condition before control automatically branches to the
interrupt handling routine. The user has to write the program only about the start and end of EI
having to code the data transfer program between them.
Advantages of extended intelligent I/O service (EI
Compared with data transfer by the interrupt handling routine, EI
advantages:
• Because no data transfer program needs to be coded, the program size can shrink.
• Because the transfer can be stopped depending the state of the peripheral function (I/O), no unnecessary
data needs to be transferred.
• Enables the user to select whether the buffer address is incremented or not updated.
• Enables the user to select whether the I/O register address is incremented or not updated.
Interrupt by extended intelligent I/O service (EI
After completion of data transfer by EI
control register (ICR) before automatic branch to the interrupt handling routine.
The cause for a stop of EI
interrupt handling program.
The interrupt numbers, interrupt vectors, etc. are fixed for individual peripheral functions. For details, see
"Section 3.2 Interrupt Cause and Interrupt Vector "
Interrupt control registers (ICR)
Located in the interrupt controller. Activates EI
2
EI OS.
Extended intelligent I/O service (EI
Located in the 000100
mode, I/O address and transfer count, and buffer address. Repeated for 16 channels. Specifies the channel
with the interrupt control register (ICR).
Note:
The CPU program execution stops while the extended intelligent I/O service (EI
74
2
OS) executes automatic data transfer between
2
OS)
2
OS) termination
2
OS, this sets the end condition in the S1 and S0 bits of the interrupt
2
OS can be determined by checking the EI
2
2
OS) descriptor (ISD)
to 00017F area in RAM. Contains a set of 8-byte data used to store the transfer
H H
2
OS executes data exchange with the
2
OS)
2
OS provides the user with the following
2
OS status (S1 and S0 of ICR) with the
OS, specifies the channel, and displays the at end state of
2
OS)
2
OS executes automatic data
2
OS without
2
OS).