Operation Of Watch Timer - Fujitsu F2MC-16LX Hardware Manual
16-bit microcontroller mb90330 series
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Also See for F2MC-16LX:
- Hardware manual (598 pages) ,
- Application note (13 pages) ,
- Operation manual (10 pages)
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CHAPTER 11 WATCH TIMER
11.4
Operation of Watch Timer
The watch timer functions as s clock source for the watchdog timer, a timer for sub
clock oscillation stabilization delay time and an interval timer that generates an
interrupt at regular intervals.
Watch Counter
The watch counter is a 15-bit counter that counts sub clock and continues counting while sub clock is input.
Clearing Watch Counter
The watch counter is cleared upon a power-on reset, change to stop mode and writing "0" to the watch
counter clear bit (WTR) of the watch timer control register (WTC).
Notes:
•
The watchdog timer and interval interrupts that use the output of the watch timer effect on the
operation by clearing the watch counter.
•
To clear the watch timer by writing "0" to the WTR bit in the watch timer control register (WTC),
set the WTIE bit to "0" and set the watch timer to interrupt inhibited state. Before permitting an
interrupt, clear the interrupt request issued by writing "0" to the WTOF flag.
Interruption Function of Interval of Watch Timer
A carry-up signal from the watch counter causes an interrupt at regular intervals.
Specification of Interval Time
The (WTC2, WTC1 and WTC0) bits of the WTC register specifies interval time.
Generation of Watch timer interrupt
The watch timer interrupt request flag bit (WTOF) is set for each interval time set by the WTC2, WTC1
and WTC0 bits. In this case, if interrupt is enabled by setting "1" in the watch timer interval interrupt
enable bit (WTIE), a watch timer interrupt is generated.
The WTOF bit is set, based on the time the watch timer was cleared last.
Because, in stop mode, the watch timer functions as a timer for sub clock oscillation stabilization delay
time, the WTOF bit is cleared immediately when mode is changed to stop mode.
Specification Function of Clock Source of Watchdog Timer
The clock source of the watchdog timer can be specified by the watchdog timer clock source selection bit
(WDCS) of the WTC register. However, when clock mode is sub clock mode, the counter value of the
watch timer is used, regardless of the value of the WDCS bit.
Sub Clock Oscillation Stabilization Delay Time Function
When recovering from power-on reset or stop mode, the watch timer functions as a timer for sub clock
oscillation stabilization delay time. The sub clock oscillation stabilization delay time is fixed to 2
clock cycles.
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