Clock Generator - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 4 GENERATING AND RESETTING CLOCKS
4.1

Clock Generator

The clock generator controls internal clock operations such as the sleep, watch, and
stop modes and the PLL clock multiplication function. This internal clock is called the
machine clock. One cycle of the machine clock is used as a machine cycle. The clock
generated by OSC oscillation is called the main clock. The clock generated by internal
VCO oscillation is called the PLL clock.
■ Notes as to the Clock Generator
When the operating voltage is 5 V, the OSC oscillation frequency range is from 3 to 16 MHz, but
the maximum operating frequency of the CPU and peripheral circuits is 16 MHz.
frequency generated by the specified multiplication factor exceeds the maximum operating
frequency, the CPU and peripheral resource circuits do not operate normally. For example, if
the OSC oscillation frequency is 16 MHz, only 1 can be specified as the multiplication factor.
The minimum operating frequency of VCO oscillation is 8 MHz. Any frequency less than this
frequency cannot be specified.
Reset
S
Interrupt
HST
R
Transition
to the stop
mode
Oscillation
stabilization
time selection
82
Figure 4.1-1 Clock Generator Block Diagram
Q
S
Transition
Q
to the watch
R
or sleep mode
Q
S
R
1/2
X0 X1
Machine clock selection
1 2
3
PLL multiplication
Time-based timer
1/2048 1/4
If the
Machine clock
4
1/4 1/8
Watchdog
interval
selection
Monitoring timer
Watchdog reset