Registers And Register Details; Lpmcr (Low Power Mode Control Register); Chapter 6 Low Power Control Circuit - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

6.3 Registers and register details

Clock selection register
Address: 0000A1
Read/write
Initial value
Low power mode control register
Address: 0000A0
Read/write
Initial value

6.3.1 LPMCR (Low power mode control register)

Low power mode control register
Address: 0000A0
Read/write
Initial value
[Bit 7] STP
Writing a "1" to this bit changes the mode to pseudo-watch mode (CKSCR. MCS = 0 and SCS = 1) or
stop mode (CKSCR. MCS = 1 or SCS = 0). Writing a "0" to this bit has no effect. This bit is cleared to
"0" by a reset, wake-up from watch or stop mode. This bit is a write-only bit. When this bit is read, "0"
is always returned.
[Bit 6] SLP
Writing a "1' to this bit changes the mode to sleep mode. Writing a "0" to this bit has no effect. This bit
is cleared to "0" by a reset, wake-up from sleep or stop mode.
If a "1' is written to both the STP bit and the SLP bit simultaneously, the mode changes to either
pseudo-watch mode or to stop mode. This bit is a write-only bit. When this bit is read, "0" is always
returned.
[Bit 5] SPL
When this bit is "0", the level of external pins in watch mode or stop mode is retained. When this bit is
"1", the external pins in watch mode or stop mode go to high-impedance. This bit is cleared to "0" by a
reset. This bit can be read and written.
MB90580 Series
15 14
SCM MCM WS1
H
(R) (R) (R/W)
(1) (1)
7 6
STP SLP
H
(W) (W)
(0) (0)
7 6
STP SLP
H
(W) (W)
(0) (0)
13 12 11
WS0 SCS
(R/W) (R/W)
(1) (1) (1)
5 4 3
SPL RST
TMD
(R/W) (W) (W)
(0) (1) (1)
5 4 3
SPL RST
TMD
(R/W) (W) (W)
(0) (1) (1)
Chapter 6: Low Power Control Circuit
6.3 Registers and register details
10 9 8
CS0
MCS CS1
(R/W) (R/W) (R/W)
(1) (0) (0)
2 1 0
CG1 CG0 SSR
(R/W) (R/W) (R/W)
(0) (0) (0)
2 1 0
CG1 CG0 SSR
(R/W)
(R/W) (R/W)
(0) (0) (0)
Bit No.
CKSCR
Bit No.
LPMCR
Bit No.
LPMCR
63