Table of Contents
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Numerics
/VFLS, 21-36
IWP, 21-36
VF, 21-3
VFLS, 21-36
/MPIO32B, 21-36
MPIO32B, 21-36
A
access violation detection, 4-5
Accesses
clock requirements, 13-52, 14-53
ACKERR, 16-36
Acknowledge error (ACKERR), 16-36
ADDR[8:31], 9-4, 9-38
Address
-mark wakeup, 15-63
address bus, 9-38
Address space, 13-10
address type (AT[0:3]),, 9-39
ALE, 21-49
ALEE, 21-51
Alignment exception, 3-53
ALU–BFU, 3-6
Analog
front-end multiplexer, 13-35, 14-37
input
considerations, 13-74, 14-75
pins, 13-72, 14-74
power pins, 13-68, 14-69
reference pins, 13-72, 14-74
section contents, 13-3, 14-3
submodule block diagram, 13-33, 14-36
supply
filtering and grounding, 13-70, 14-71
pins, 13-68, 14-69
to digital converter operation, 13-32, 14-36
arbitration,, 9-32
AT[0:3], 9-4
atomic, 9-32
atomic operation
reservation of data, 11-8
atomic update primitives,, 3-46
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Index
B
BAR, 3-64, 21-61
Base ID mask bits, 16-33, 16-34, 16-35
Baud
clock, 15-56
BB, 9-7
BBCMCR, 4-16
BDIP,, 9-5
BE bit, 3-23
Beginning of queue 2 (BQ2), 13-17, 14-20
BG, 9-7
BI, 9-7, 9-42
Binary
divider, 13-48, 14-50
-weighted capacitors, 13-35, 14-37
Bit stuff error (STUFFERR), 16-36
BITERR, 16-36
BITS, 15-19
Bits per transfer
enable (BITSE), 15-25
field (BITS), 15-19
BITSE, 15-25, 15-42
Bit-time, 15-55
BIU, 13-3, 13-51, 14-3, 14-53
BIUSM
BIUTEST — BIUSM test configuration register,
17-12
selecting the time base bus, 17-12
BIUTEST — BIUSM test configuration register,
17-12
block diagram
CALRAM, 20-2
JTAG test logic, 23-3
L2U, 11-3
memory controller, 10-2
MPC533, 1-2
READI, 22-3
READI signal interface, 22-24
TouCAN, 16-1
UC3F EEPROM, 19-1
UIMB, 12-2
USIU, 6-3
block diagrams
analog subsystem, 13-33
Index
Index-1
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