Motorola MPC533 Reference Manual page 1188

PVR, 3-28
Q
QACR0, 13-7, 13-14, 14-8
QACR1, 13-7, 13-14, 14-8, 14-17
QACR2, 13-7, 13-16, 14-8, 14-19
QADC64E conversion queue operation, 14-30
QADC64E module configuration register
(QADCMCR), 13-6
QADCINT, 13-7, 13-11, 14-12
QADCMCR, 13-6, 13-7, 14-8
QADCTEST, 13-7
QADMCR, 13-7
QASR, 13-7, 13-19, 14-8, 14-22
QCLK, 13-47, 14-49
frequency, 13-48, 14-50
QDDR, 15-14, 15-45
QILR, 15-9
QPAR, 15-12
QPDR, 15-12, 15-45
QS, 13-23, 14-25
QSCI1 registers
QSCI1CR, 15-64
QSCI1SR, 15-64
QSM
global registers, 15-6
pin function, 15-11
QSPI, 15-15
operating modes, 15-28
operation, 15-26
RAM, 15-23
registers
pin control registers, 15-10
port QS
data
data register (PORTQS)
QSCI
control register 1 (QSCI1CR), 15-64
status register 1 (QSCI1SR), 15-64
QSPI
control register 0 (SPCR0), 15-18
control register 1 (SPCR1), 15-20
control register 2 (SPCR2), 15-20
control register 3 (SPCR3), 15-21
status register (SPSR), 15-21
SCI
control register 0 (SCCR0), 15-49
control register 1 (SCCR1), 15-49
data register (SCDR), 15-53
status register (SCSR), 15-51
SCI, 15-45
operation, 15-54
Index-10
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
direction register
(DDRQS)
, 15-11
, 15-11
MPC533 Reference Manual
pins, 15-54
registers, 15-48
QSM Data Direction Register (QDDR), 15-14, 15-45
QSM Interrupt Level Register (QILR), 15-9
QSM Pin Assignment Register (QPAR), 15-12
QSM Port Data Register (QPDR), 15-12, 15-45
QSMCMMCR bit settings, 15-9
QSPI, 15-15
block diagram, 15-16
enable (SPE), 15-20
finished flag (SPIF), 15-22
initialization operation, 15-30
loop mode (LOOPQ), 15-22
master operation flow, 15-31
operating modes, 15-28
master mode, 15-28, 15-36
wraparound mode, 15-41
slave mode, 15-28, 15-41
operation, 15-26
peripheral chip-selects, 15-39
RAM, 15-23, 15-24
command RAM, 15-24
receive RAM, 15-24
transmit RAM, 15-24
QSPI Enable (SPE), 15-45
QSPI Status Register (SPSR), 15-45
Queue, 13-36, 14-39
1 completion flag (CF1), 13-20, 14-22
1 completion interrupt enable (CIE1), 13-14, 14-17
1 operating mode (MQ1), 13-15, 14-18
1 pause flag (PF1), 13-20, 14-23
1 pause interrupt enable (PIE1), 13-14, 14-17
1 single-scan enable bit (SSE1), 13-15, 14-17
1 trigger overrun (TOR1), 13-22, 14-24
2 completion flag (CF2), 13-21, 14-23
2 completion software interrupt enable (CIE2),
13-16, 14-19
2 operating mode (MQ2), 13-17, 14-20
2 pause flag (PF2), 13-21, 14-24
2 pause software interrupt enable (PIE2), 13-16,
14-19
2 single-scan enable bit (SSE2), 13-17, 14-19
2 trigger overrun (TOR2), 13-22, 14-25
pointers
completed queue pointer (CPTQP), 15-26
end queue pointer (ENDQP), 15-26
new queue pointer (NEWQP), 15-26
priority, 13-36, 14-39
priority schemes, 13-54, 13-64, 14-55, 14-65
status (QS), 13-23, 14-25
queue
SCI, 15-63
Queued
serial
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