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K.14 QADC64E Electrical Characteristics
Table K-16. QADC64E Conversion Characteristics
= 2.6 V ± 0.1 V, V
Note: (V
DD
Num
97
QADC Clock (QCLK) Frequency
98
Conversion Cycles
QADCMCR
99
Conversion Time
1
F
= 2.0 MHz
QCLK
Enhanced mode: QADCMCR
Min = CCW[IST] =0b0
Max = CCW[IST] =0b1
100
Stop Mode Recovery Time
3
101
Resolution
102
Absolute (total unadjusted) error
3
F
= 2.0MHz
QCLK
102a Absolute (total unadjusted) error
3
F
= 2.0MHz
QCLK
104
DC Disruptive Input Injection Current
105
Current Coupling Ratio
PQA
106
Incremental error due to injection current
All channels have same 10KΩ < Rs <100kΩ
Channel under test has Rs=10KΩ, I
107
Source impedance at input
107a Incremental capacitance during Sampling
1
Conversion characteristics vary with F
2
The number of conversion cycles is dependent on the IST bit in the CCW register.
3
At V
– V
= 5.12 V, one count = 5 mV.
RH
RL
4
Accuracy tested and guaranteed at V
5
This parameter is periodically sampled rather than 100% tested.
6
Absolute error includes 1/2 count (~2.5 mV) of inherent quantization error and circuit (differential, integral, and
offset) error. Specification assumes that adequate low-pass filtering is present on analog input pins — capacitive filter
with 0.01 µF to 0.1 µF capacitor between analog input and analog ground, typical source isolation
impedance of 10 KΩ.
7
Input signals with large slew rates or high frequency noise components cannot be converted accurately. These signals
may affect the conversion accuracy of other channels.
8
Accuracy tested and guaranteed at V
K-7.
9
This parameter is periodically sampled rather than 100% tested.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
= 5.0 V ± 0.25 V, T
DDH
Parameter
1
2
4, 5, 6, 7
, 2 clock input sample time
8, 9, 10, 11
, 2 clock input sample time
12, 13, 14, 15, 16
19
=+3mA
INJ
20
21
rate. Reduced conversion accuracy occurs at max F
QCLK
– V
= 5.0 V ± 0.25 V
RH
RL
– V
= 1.0V to 0.75 x V
ARH
RL
Appendix K. Electrical Characteristics
QADC64E Electrical Characteristics
= T
to T
)
A
L
H
Symbol
F
QCLK
CC
T
SR
—
AE
AE
ALT
17
I
INJ
18
I
INJ
K
E
INJ
R
S
C
SAMP
V. See Specification 52 in Table K-4 on page
DDA
Min
Max
0.5
3.0
14
20
QCLK cycles
7.0
10
—
10
5
—
-2
2
-7.8
3.5
-3
3
-1
1
-5
—
8x10
+1.0
+1.0
—
100
—
5
rate.
QCLK
Units
MHz
µs
µs
µs
mV
Counts
mV
mΑ
mA
Counts
Counts
KΩ
pF
K-55
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