Motorola MPC533 Reference Manual page 1187

Open drain drivers, 14-69
operand placement (effects),, 3-47
operand representation (illustration),, 9-30
Operating Environment Architecture (Book 3)
branch processor,, 3-48
exceptions,, 3-48
fixed-point processor
special purpose registers,, 3-48
fixed-point processor,, 3-48
optional facilities and instructions,, 3-65
storage control instructions,, 3-48
timer facilities,, 3-65
Operating Environment Architecture (OEA), 3-47
optional instructions,, 3-43
OR, 15-53
OR registers, 10-36
Ordered exceptions, 3-39
OTR, 22-8
OV (overflow) bit, 3-20
Overload frames, 16-18
OVERRUN
receive message buffer code, 16-5
Overrun error (OR), 15-53
OX bit, 3-15
P
P, 13-30, 14-32
Parity
(PF) flag, 15-61
checking, 15-56
enable (PE), 15-50
error (PF) bit, 15-53
errors, 15-61
type (PT), 15-50
type (PT) bit, 15-56
Pause (P), 13-30, 13-37, 14-32, 14-39
PCS, 15-25
to SCK delay (DSCK), 15-25
PCS0/SS, 15-42
PCS3-PCS0/SS, 15-45
PE, 15-50
performance
L-bus, 11-11
Periodic interrupt
timer, 6-21
Periodic/interval timer, 13-50, 14-52
continuous-scan mode, 13-47, 14-49
Peripheral
chip-selects (PCS), 15-25, 15-39
Peripheral Chip-Select 3-0/Slave Select
(PCS3-PCSO/SS), 15-45
PF, 15-53, 15-61
PF1, 13-20, 14-23
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
PF2, 13-21, 14-24
Phase buffer segment 1/2 (PSEG1/2) bit field, 16-32
phase-lock loop,, 9-8
PIE1, 13-14, 14-17
PIE2, 13-16, 14-19
PISCR, 6-45
PIT, 6-21
PITC, 6-46
PITR, 6-47
PLL, 8-3
loss of lock, 7-3
PLL,, 9-8
PLPRCR, 8-33
Pointer, 15-17
PORESET, 7-1
Port
A data register (PORTQA), 13-12
B data register (PORTQB), 13-12
port size device interfaces (illustration),, 9-31
port width definition, 9-2
PORTQA, 13-12
PORTQB, 13-12
PORTQS, 15-11
Positive stress, 13-77, 14-78
power on reset, 7-1
PQA, 13-67, 14-68
PQSPAR, 15-11, 15-36, 15-41
PR bit, 3-8, 3-23
PRE, 21-49
Precise exceptions, 3-40
PREE, 21-51
Prescaler, 13-48
clock high time (PSH), 13-48, 14-15
divide
factor field, 16-31
register (PRESDIV), 16-9, 16-31
PRESDIV (bit field), 16-31
PRESDIV (register), 16-9, 16-10, 16-31
priority
CALRAM overlay regions, 20-6
Privilege level, 3-8, 3-23
Processor version register, 3-28
Program, 3-55
exception, 3-55
Programmable
transfer length, 15-16
Propagation segment time (PROPSEG), 16-31
PROPSEG, 16-13, 16-31
PSEG1, 16-32
PSEG2, 16-10, 16-13, 16-32
PSEGS1, 16-13
PSH, 13-48, 14-15
PT, 15-50, 15-56
PTR,, 9-5, 9-39
Index Index-9