Motorola MPC533 Reference Manual page 1157

K.18.1 MPWMSM Timing Characteristics
Note: All delays are in system clock periods.
Characteristic
PWMSM output resolution
3
PWM output pulse
MPWMI input pin to MPWMSCR_PIN
status set
CPSM enable to output set
MPWMSM Enable to output set (MIN)
MPWMSM Enable to output set (MAX)
Interrupt Flag to output pin reset (period
7
start)
1
Minimum output resolution depends on MPWMSM and MCPSM prescaler settings.
2
Maximum resolution is obtained by setting CPSMPSL[3:0] =0x2 and MPWMSCR_CP[7:0] =0xFF.
3
Excluding the case where the output is always "0".
4
With MPWMSM enabled before enabling the MCPSM. Please also see NOTE 1 on the MCPSM timing
information.
5
The exact timing from MPWMSM enable to the pin being set depends on the timing of the register write and the
MCPSM VS_PCLK.
6
When MCPSMSCR_PSL = 0x0000, this gives a prescale value of 16 and it is 16 which should be used in these
calculations. When MCPSMSCR_PSL = 0x0001, the CPSM is inactive.
7
The interrupt is set before the output pin is reset (Signifying the start of a new period).
f
SYS
MPWMO output pin
Figure K-45. MPWMSM Minimum Output Pulse Example Timing Diagram
f is the internal system clock for the IMB3 bus.
SYS
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table K-21. MPWMSM Timing Characteristics
Symbol
t
PWMR
t
PWMO
t
PIN
4
t
PWMP
5
t
PWME
5
t
PWME
t
FLGP
t
PWMO
min
Appendix K. Electrical Characteristics
Min
1
—
2.0
1
(MPWMPERR - MPWMPULR + 1) *
(256 - MPWMSCR_CP) * MCPSMSCR_PSL + 1
(MPWMPERR - MPWMPULR) * (256 - MPWMSCR_CP) *
MCPSMSCR_PSL + 3 +
(255 - MPWMSCR_CP) * MCPSMSCR_PSL
t (MIN) + MCPSMSCR_PSL - 1
PWME
(256 - MPWMSCR_CP) * MCPSMSCR_PSL - 1
NOTE
MIOS Timing Characteristics
Max
2
2.0
—
2
6
6
6
K-63