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3-14
general
special-purpose
(SPRG0-SPRG3) 3-27
general-purpose registers (GPRs) 3-13
implementation-specific special-purpose registers
3-29
integer exception register (XER) 3-19
link register (LR) 3-20
machine state register (MSR) 3-22
machine status save/restore register 0 (SRR0)
3-26
machine status save/restore register 1 (SRR1)
3-27
OEA register set 3-22
processor version register (PVR) 3-28
UISA register set 3-13
VEA register set - time base 3-21
READI development control register 22-10, 22-12
READI device ID register 22-10
READI DID 22-10
READI DTA 1 and DTA 2 (READI data trace at-
tributes 1 and 2 registers) 22-17
READI RWA (READI read/write access register)
22-13
READI UBA (READI user base accress register)
22-12
READI UDI (READI upload/download information
register) 22-15
Region attribute register (0 - 3) 4-19
Register diagrams
CALRLAM_OTR (CALRAM ownership trace
register) 20-12
CANCTRL0 (control register 0) 16-29
CANCTRL1 (control register 1) 16-30
CANCTRL2 (control register 2) 16-32
CMPG-CMPH (comparator G-H value registers)
21-54
COUNTA (breakpoint counter A value and con-
trol register) 21-53
CRAM_RBAx (CALRAM region base address
register) 20-10
CRAMMCR (CALRAM module configuration
register) 20-8
CRAMOVL (CALRAM overlay configuration
register) 20-11
DDRQS (PORTQS data direction register) 15-14
DEC (decrementer register) 3-26
DER (debug enable register) 21-51
ECR (exception cause register) 21-49
EIBADR (external interrupt relocation table base
address register) 4-22
IMASK (interrupt mask register) 16-37
L2U_GRA (L2U global region attribute register)
11-17
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
registers
Registers
Register General and Diagram Index
L2U_MCR (L2U module configuration register)
11-15
L2U_RAx (L2U region X attribute register) 11-16
L2U_RBAx (L2U region x base address register)
11-16
LCTRL2 (L-bus support control register 2) 21-56
MIOS14SR0 (interrupt status register) 17-66
MIOS14SR1 (interrupt status register) 17-68,
17-69
MIOS1LVL0 (MIOS1 interrupt level register 0)
17-70
MIOS1LVL1 (MIOS1 interrupt level 1 register)
17-70
MISCNT (MISC counter) 19-5, 19-8
PORTQS (port QS data register) 15-12
PQSPAR (PORTQS pin assignment register)
15-13
PRESDIV (prescaler divide register) 16-31
QACR1 (QADC64E control register 1) 13-14,
14-17
QADCMCR (module configuration register) 13-7
QSCI1CR (QSCI1 control register) 15-64
QSCI1SR (QSCI1 status register) 15-65
QSMCMMCR (QSMCM module configuration
register) 15-9
QSPI_IL (QSPI interrupt level register) 15-10
READI DTA 1 and DTA 2 (READI data trace at-
tributes 1 and 2 registers) 22-17
Region attribute register (0 - 3) 4-19
SCCxR0 (QSMCM SCI control register 0) 15-49
SCCxR1 (QSMCM SCI control register 1) 15-50
SCDR (QSMCM SCI data register) 15-54
SCxSR (QSMCM SCIx status register) 15-52
SPCR0 (QSPI control register 0) 15-18
SPCR1 (QSPI control register 1) 15-20
SPCR2 (QSPI control register 2) 15-21
SPCR3 (QSPI control register) 15-21
SPRG0-SPRG3 (general special-purpose regis-
ters 0-3) 3-28
SPSR (QSPI status register) 15-22
SRR0 (machine status save/restore register 0)
3-26, 3-27
TBREF1 (time base reference register 1) 6-43
UC3FCFIG (hard reset configuration word) 19-16
UC3FCTL (UC3F EEPROM high voltage control
register 19-11
UIPEND (UIMB pending interrupt reqiuest regis-
ter) 12-9
UMCR (UIMB module configuration register)
12-8
XER (integer exception register) 3-19
Associated registers 10-4
BAR (breakpoint address register) 21-61
RegIndex-3
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