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6-46
PITR (periodic interrupt timer register) 6-47
PLPRCR (PLL, low-power, and reset-control reg-
ister) 8-33
Port data direction registers 13-13, 14-14
Port data registers 13-12, 14-14
PPMMCR (module confguration register) 18-10
PPMPCR (PPM control register) 18-11
QACR0 (QADC64E control register 0) 13-13,
14-15
QACR1 (QADC64E control register 1) 13-14,
14-17
QACR2 (QADC64E control register 2) 13-16,
14-19
QADCINT (QADC64E interrupt register) 13-11,
14-12
QADCMCR (module configuration register) 14-8
QASR (status register 0) 14-22
QASR (status registers) 13-19
QSMCM
configuration register (QMCMMCR) 15-9
interrupt
level
QSPI_IL) 15-9
port QS data register (PORTQS) 15-12
PORTQS data direction register (DDRQS)
15-14
PORTQS pin assignment register (PQSPAR)
15-12
QSCI1 control register (QSCI1CR) 15-64
QSCI1 status register (QSCI1SR) 15-65
QSPI command RAM (CRx) 15-24
QSPI control register 0 (SPCR0) 15-18
QSPI control register 1 (SPCR1) 15-20
QSPI control register 2 (SPCR2) 15-20
QSPI control register 3 (SPCR3) 15-21
QSPI registers 15-17
QSPI status register (SPSR) 15-22
queued SCI1 status and control registers
15-64
SCI control register 0 (SCCxR0) 15-49
SCI control register 1 (SCCxR1) 15-49
SCI data register (SCxDR) 15-53
SCI registers 15-48
SCI status register (SCxSR) 15-51
test register (QTEST) 15-9
RCPU
additional implementation-specific registers
3-30
condition register (CR) 3-17
condition register CR0 field definition 3-18
condition register CR1 field definition 3-18
condition register crn field - compare instruc-
tion 3-19
count register (CTR) 3-21
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
registers
(QDSCI_IL,
Register General and Diagram Index
dae/source
instruction
(DSISR) 3-24
data address register (DAR) 3-25
decrementer register (DEC) 3-26
EIE, EID, and NRI special-purpose registers
3-29
floating-point exception cause register (FPE-
CR) 3-29
floating-point registers (FPRs) 3-13
floating-point status and control register (FP-
SCR) 3-14
general
special-purpose
(SPRG0-SPRG3) 3-27
general-purpose registers (GPRs) 3-13
implementation-specific special-purpose reg-
isters 3-29
integer exception register (XER) 3-19
link register (LR) 3-20
machine state register (MSR) 3-22
machine status save/restore register 0 (SRR0)
3-26
machine status save/restore register 1 (SRR1)
3-27
OEA register set 3-22
processor version register (PVR) 3-28
UISA register set 3-13
VEA register set - time base 3-21
READI development control register 22-10,
22-12
READI DID 22-10
READI DTA 1 and DTA 2 (READI data trace at-
tributes 1 and 2 registers) 22-17
READI RWA (READI read/write access register)
22-13
READI UBA (READI user base address register)
22-12
READI UDI (READI upload/download informa-
tion register) 22-15
RSR (reset status register) 7-5
RTC (real-time clock register) 6-45
RTCAL (real-time clock alarm register) 6-45
RTCSC (real-time clock status and control regis-
ter) 6-44
Rx_config_1 (Rx configuration register 1) 18-15
Rx_Config_2 (Rx configuration register 2) 18-15
Rx_data register 18-16
Rx_shifter register 18-17
RXECTR (receive error counter) 16-38
SCALE_TCLK_REG (scale tclk register) 18-21
SCCR (system clock control register) 8-29
SGPIO
control register (SGPIOCR) 6-49
data register 1 (SGPIODT1) 6-47
data register 2 (SGPIODT2) 6-48
service
register
registers
RegIndex-5
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