Motorola MPC533 Reference Manual page 1190

CRAMOVL CALRAM overlay configuration
register, 20-11
DAE/source instruction service register (DSISR),
3-24
data address register (DAR), 3-25
DCCR0-DCCR15 decompressor class
configuration registers, A-24
debug enable register (DER), 21-50
decompressor class configuration, 4-23
decrementer register (DEC), 6-41
development port data register (DER), 21-61
documenter register (DEC), 3-26
dual-mapping base register (DMBR), 10-38
dual-mapping option register (DMOR), 10-39
EIBADR external interrupt relocation table base
address register, 4-22
exception cause register (ECR), 21-49
external master control register (EMCR), 6-30
floating point (FPRs), 3-13
floating point exception cause register (FPECR),
3-29
floating point status and control register (FPSCR),
3-14
general purpose registers (GPRs), 3-13
general SPRs, 3-27
hard reset configuration word register (UC3FCFIG),
19-16
I-bus support control register (COUNTA), 21-58
I-bus support control register (ICTRL), A-21
implementation specific SPRs, 3-29
integer exception register (XER), 3-19
internal memory map register (IMMR), 6-29
interrupt (QADCINT), 13-11, 14-12
interrupt in-service registers (SISR2 and SISR3),
6-38
L2U global region attribute registers (L2U_GRA),
11-17
L2U module configuration register (L2U_MCR),
11-15
L2U region attribute registers (L2U_RAx), 11-16
L2U region base address registers (L2U_RBAx),
11-15
L-bus support control register 1 (LCTRL1), 21-55
L-bus support control register 2 (LCTRL2), 21-56
left justified, unsigned result format (LJURR),
13-31, 14-35
link register (LR), 3-20
machine state (MSR), 3-22
machine status save/restore register 0 (SRR0), 3-26
machine status save/restore register 1 (SRR1), 3-27
memory controller base registers (BR0-BR3), 10-34
memory controller option registers (OR0-OR3),
10-36
memory controller status registers (MSTAT), 10-34
Index-12
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MI_GRA global region atribute register, 4-21
MI_RA [0:3] region attribute register, 4-19
MI_RBA[0:3] region base address register, 4-18
module configuration (QADC64E), 13-7
pending interrupt request register (UIPEND), 12-9
periodic interrupt status and control register
periodic interrupt timer count register (PITC), 6-46
periodic interrupt timer register (PITR), 6-47
PLL, low power, and reset control register
port A data register (PORTQA), 13-12
port B data register (PORTQB), 13-12
processor version register (PVR), 3-28
QACR0 control register, 13-14, 14-15
QADC64E control register 1 (QACR1), 13-14,
QADC64E control register 2 (QACR2), 13-16,
QADC64E module configuration (QADCMCR),
QADC64E PORTQA Port A data register, 14-14
QADC64E PORTQA port A data register, 13-13
READI data trace attribute 1 register (DTA1), 22-17
READI data trace attribute 2 register (DTA2), 22-17
READI development control register (DC), 22-10
READI device ID register (DID), 22-10
READI mode control register (MC), 22-12
READI ownership trace register (OTR), 22-8
READI read/write access register (RWA), 22-13
READI upload/download information register
READI user base address register (UBA), 22-12
real-time clock alarm register (RTCAL), 6-45
real-time clock register (RTC), 6-45
real-time clock status and control register (RTCSC),
receive mask, 16-7
reset status register (RSR), 7-5
SGPIO control register (SGPIOCR), 6-49
SGPIO data register 1 (SGPIODT1), 6-47
SGPIO data register 2 (SGPIODT2), 6-48
SIU interrupt edge level register (SIEL), 6-36
SIU interrupt mask registers (SIMASK), 6-34
SIU interrupt vector register (SIVEC), 6-36
SIU module configuration register (SIUMCR), 6-26
software service register (SWSR), 6-40
special purpose, 3-48
added registers,, 3-48
unsupported registers,, 3-48
status (QASR), 13-19, 14-22
status (QASR0), 13-19, 14-22
status (QASR1), 13-26, 14-28
MPC533 Reference Manual
(PISCR), 6-45
(PLPRCR), 8-33
14-17
14-19
14-8
(UDI), 22-15
6-44
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