Motorola MPC533 Reference Manual page 1172

module and version
(MIOS1VNR) 17-13
MIOS14ER0 interrupt enable register 17-66
MIOS14ER1 interrupt enable register 17-68
MIOS14MCR (MIOS14 module configuration regis-
ter) 17-13
MIOS14RPR0 request pending register 17-67
MIOS14RPR1 request pending register 17-68
MIOS14SR0 (interrupt status register) 17-66
MIOS14SR0 interrupt status register 17-66, 22-8
MIOS14SR1 (interrupt status register) 17-68, 17-69
MIOS14SR1 interrupt status register 17-67
MIOS14TPCR (test and pin control register) 17-12
MIOS1LVL0 (MIOS1 interrupt level register 0) 17-70
MIOS1LVL1 (MIOS1 interrupt level 1 register) 17-70
MISCNT (MISC counter) 19-5, 19-8
MMCSMCNT (MMCSM up-counter register) 17-23
MMCSMMML (MMCSM modulus latch register)
17-23
MMCSMSCR (MMCSM status/control register)
17-24
MPIOSMDDR (MPIOSM data direction register)
17-63
MPIOSMDR (MPIOSM data register) 17-63
MPWMCNTR (MPWMSM counter register) 17-57
MPWMPERR (MPWMSM period register) 17-57
MPWMPULR (MPWMSM pulse width register)
17-57
MPWMSCR (MPWMSM status/control register)
17-58
MSTAT (memory controller status registers) 10-34
O
OR0 - OR3 (memory controller option registers 0-3)
10-36
P
PDMCR (pads module configuration register) 2-23
PDMCR2 (pads module configuration register) 2-24
PISCR (periodic interrupt status and control register)
6-45
PITC (periodic interrupt timer count register) 6-46
PITR (periodic interrupt timer register) 6-47
PLPRCR (PLL, low-power, and reset-control register)
8-33
Port data direction registers 13-13, 14-14
Port data registers 13-12, 14-14
PORTQS (port QS data register) 15-12
PPMMCR (module configuration register) 18-10
PPMPCR (PPM control register) 18-11
PQSPAR (PORTQS pin assignment register) 15-13
PRESDIV (prescaler divide register) 16-31
Q
QACR0 (QADC64E control register 0) 13-13, 14-15
QACR1 (QADC64E control register 1) 13-14, 14-17
RegIndex-2
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
number register
MPC533 Reference Manual
QACR2 (QADC64E control register 2) 13-16, 14-19
QADCINT (QADC64E interrupt register) 13-11,
14-12
QADCMCR (module configuration register) 13-7,
14-8
QASR (status register 0) 14-22
QASR (status registers) 13-19
QSCI1CR (QSCI1 control register) 15-64
QSCI1SR (QSCI1 status register) 15-65
QSMCM
configuration register (QMCMMCR) 15-9
interrupt level registers (QDSCI_IL, QSPI_IL)
15-9
port QS data register (PORTQS) 15-12
PORTQS data direction register (DDRQS) 15-14
PORTQS pin assignment register (PQSPAR)
15-12
QSCI1 control register (QSCI1CR) 15-64
QSCI1 status register (QSCI1SR) 15-65
QSPI command RAM (CRx) 15-24
QSPI control register 0 (SPCR0) 15-18
QSPI control register 1 (SPCR1) 15-20
QSPI control register 2 (SPCR2) 15-20
QSPI control register 3 (SPCR3) 15-21
QSPI registers 15-17
QSPI status register (SPSR) 15-22
queued SCI1 status and control registers 15-64
SCI control register 0 (SCCxR0) 15-49
SCI control register 1 (SCCxR1) 15-49
SCI data register (SCxDR) 15-53
SCI registers 15-48
SCI status register (SCxSR) 15-51
test register (QTEST) 15-9
QSMCMMCR (QSMCM module configuration regis-
ter) 15-9
QSPI_IL (QSPI interrupt level register) 15-10
R
RCPU
additional implementation-specific registers 3-30
condition register (CR) 3-17
condition register CR0 field definition 3-18
condition register CR1 field definition 3-18
condition register crn field - compare instruction
3-19
count register (CTR) 3-21
dae/source instruction service register (DSISR)
3-24
data address register (DAR) 3-25
decrementer register (DEC) 3-26
EIE, EID, and NRI special-purpose registers 3-29
floating-point exception cause register (FPECR)
3-29
floating-point registers (FPRs) 3-13
floating-point status and control register (FPSCR)
MOTOROLA