Motorola MPC533 Reference Manual page 1142

RESET Timing
K.12 RESET Timing
= 2.6 V ± 0.1 V, V
Note: (V
DD
43 CLKOUT to HRESET high impedance
44 CLKOUT to SRESET high impedance
45 RSTCONF pulse width
46 Configuration Data to HRESET rising edge Setup Time
47 Configuration Data to RSTCONF rising edge set up time
48 Configuration Data hold time after RSTCONF negation
49 Configuration Data hold time after HRESET negation
49a RSTCONF hold time after HRESET negation
50 HRESET and RSTCONF asserted to Data out drive
51 RSTCONF negated to Data out high impedance
52 CLKOUT of last rising edge before chip tristates HRESET to Data
out high impedance
53 DSDI, DSCK set up
54 DSDI, DSCK hold time
55 SRESET negated to CLKOUT rising edge for DSDI and DSCK
sample
55a HRESET, SRESET, PORESET pulse width
Weak pull-ups and pull-downs used for Reset timing will comply with the 130 µA mode select current outlined in
1
Table K.5 on page K-7 The system requires two clocks of hold time on
RSTCONF/TEXP after negation of HRESET. The simplest way to insure meeting this requirement in systems that
require the use of the TEXP function, is to connect RSTCONF/TEXP to SRESET.
2
HRESET, SRESET and PORESET have a glitch detector to ensure that spikes less than 20 ns are rejected. The internal
HRESET, SRESET and PORESET will assert only if these signals are
asserted for more than 100 ns
K-48
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table K-14. RESET Timing
= 5.0 V ± 0.25 V, T
= T
DDH A
Characteristic
1
2
MPC533 Reference Manual
to T )
L H
Expression
17 * TC
15 * TC + TCC
15 * TC + TCC
3 * TC
8 * TC
40 MHz
Unit
Min Max
20 ns
20 ns
425 ns
382 ns
382 ns
0 ns
0 ns
50
25 ns
25 ns
25 ns
75 ns
0 ns
200 ns
100 ns
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