Motorola MPC533 Reference Manual page 1159

K.18.2 MMCSM Timing Characteristics
Note: All delays are in system clock periods.
Characteristic
MMCSM input pin period
MMCSM pin low time
MMCSM pin high time
clock pin to counter bus increment.
load pin to new counter bus value
clock pin to PINC delay
Load pin to PINL delay
Counter bus resolution
Counter bus overflow reload to interrupt flag
MCPSM enable to counter bus increment.
MMCSM Enable to counter bus increment
3
(MIN)
MMCSM Enable to counter bus increment
3
(MAX)
1
Minimum output resolution depends on MMCSM and MCPSM prescaler settings.
2
Maximum resolution is obtained by setting CPSMPSL[3:0] =0x2 and MMCSMSCR_CP[7:0] =0xFF.
3
The exact timing from MMCSM enable to the pin being set depends on the timing of the MMCSMSCR register write
and the MCPSM VS_PCLK. The MMCSM enable is taken to mean the MMCSMSCR_CLS[1:0] being written to
2'b11.
f
SYS
MMCSM pin
Figure K-49. MMCSM Minimum Input Pin (Either Load Or Clock) Timing Diagram
f is the internal system clock for the IMB3 bus.
SYS
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table K-22. MMCSM Timing Characteristics
Symbol
t
t
t
t
CBFLG
t
t
t
t
PPER
min
Appendix K. Electrical Characteristics
Min
4
PPER
t 2
PLO
t 2
PHI
1
PCCB
1
PLCB
t 1
PINC
t 1
PINL
1
t —
CBR
(256 - MMCSMSCR_CP) * MCPSMSCR_PSL + 2
MCMP
4 + MCPSMSCR_PSL*
MCME
(255 - MMCSMSCR_CP)
4 + MCPSMSCR_PSL * (255 - MMCSMSCR_CP)
MCME
+ (MCPSMSCR_PSL - 1)
t
PLO
min
NOTE
MIOS Timing Characteristics
Max
—
—
—
2
2
2
2
2
2
1
3
3
t
PHI
min
K-65