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f
SYS
MMCSMSCR_CLS[1:0]
Counter bus[15:0]
Figure K-53. MMCSM Prescaler Clock Select To Counter Bus Increment
K.18.3 MDASM Timing Characteristics
Note: All delays are in system clock periods.
Characteristics
MDASM input pin period
MDASM pin low time
MDASM pin high time
Input capture resolution
Input pin to Counter Bus capture delay
Input pin to interrupt flag delay
Input pin to PIN delay
Counter bus resolution
3
Output pulse width
3
Compare resolution
Counter Bus to pin change
Counter Bus to interrupt flag set.
1
If the counter bus capture occurs when the counter bus is changing then the capture is delayed one cycle. In
situations where the counter bus is stable when the input capture occurs the t
cycles (the one-cycle uncertainty is due to the synchronizer).
2
Maximum resolution is obtained by setting CPSMPSL[3:0] =0x2 and MDASMSCR_CP[7:0] =0xFF.
3
Maximum output resolution and pulse width depends on counter (e.g., MMCSM) and MCPSM prescaler
settings.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
1
2
3
4
1
00
11
Timing Diagram
Table K-23. MDASM Timing Characteristics
Symbol
Input Modes: (IPWM, IPM, IC, DIS)
Output Modes: (OC, OPWM)
t
Appendix K. Electrical Characteristics
t
MCME
A
Min
t
4
PPER
t
2
PLO
t
2
PHI
t
—
CAPR
t
1
PCAP
t
2
PFLG
t
1
PIN
t
—
CBR
t
2
PULW
t
—
COMR
t
CBP
CBFLG
MIOS Timing Characteristics
A+1
Max
—
—
—
2
1
3
3
2
2
2
—
2
2
3
3
has a maximum delay of two
PCAP
K-67
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