Motorola MPC533 Reference Manual page 1156

MIOS Timing Characteristics
1
AC timing is shown is tested to the 3-V levels outlined in Table K-4 on page K-7.
K.18 MIOS Timing Characteristics
All MIOS output pins are slew rate controlled. Slew rate control circuitry adds 90 ns as
minimum to the output timing and 650 ns as a maximum. This slew rate is from 10% V
to 90% V , an additional 100 ns should be added for total 0 to V
DD
Note: After reset MCPSMSCR_PSL[3:0] is set to 0b0000.
Note: VS_PCLK is the MIOS prescaler clock which is distributed to all the counter (e.g., MPWMSM and
MMCSM) submodules.
Characteristic
MCPSM enable to VS_PCLK pulse
1
The MCPSM clock prescaler value (MCPSMSCR_PSL[3:0]) should be written to the MCPSMSCR (MCPSM
Status/Control Register) before rewriting the MCPSMSCR to set the enable bit (MCPSMSCR_PREN). If this is not
done the prescaler will start with the old value in the MCPSMSCR_PSL[3:0] before reloading the new value into the
counter.
f
SYS
Prescaler enable
bit (PREN)
MIOB VS_PCLK
Note 1: f is the internal system clock for the IMB3 bus.
SYS
Note 2: The numbers associated with the f
Note 3: vs_pclk is the MIOS prescaler clock which is distributed around the MIOS to counter modules such as the
MMCSM and MPWMSM.
Figure K-44. MCPSM Enable to VS_PCLK Pulse Timing Diagram
K-62
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table K-20. MCPSM Timing Characteristics
Symbol
1
t
CPSMC
t
CPSMC
ticks refer to the IMB3 internal state.
SYS
MPC533 Reference Manual
slew rate.
DD
Delay
(MCPSMSCR_PSL[3:0]) -1
DD
Unit
System Clock
Cycles
MOTOROLA