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(d) DMA flyby transfer timing (SRAM → external I/O)
Figure 1-6. DMA Flyby Transfer Timing (SRAM → External I/O)
BUSCLK (output)
A0-A25, CSZ0-CSZ7
(output)
RDZ (output)
WRZ0-WRZ3, WRSTBZ
(output)
IORDZ (output)
IOWRZ (output)
D0-D31 (I/O)
WAITZ (input)
< t
BCYSTZ (output)
Note
In the case of CSZ0-CSZ7
Remarks 1. Timing when the number of waits inserted by the DWC0 or DWC1 register is 0, the
number of idle states inserted by the BCC register is 1, and the number of waits inserted
by the ASC register is 1.
2.
Broken lines indicate high impedance
CHAPTER 1 PRODUCT SPECIFCATIONS
TASW
T1
< t
>
DKA
< t
>
DKRDH
< t
>
DKWRH
< t
>
DKRDH
< t
>
DKWRH
< t
>
HKW
< t
>
SKW
>
< t
DKBSL
DKBSH
User's Manual A19069EJ2V0UM
TW
T2
< t
>
DKRDL
< t
>
< t
DKWRL
DKWRH
< t
>
HKW
< t
>
SKW
>
TF
TI
< t
DKA
Note
< t
>
DKRDH
>
< t
>
HKOD
< t
>
DKBSL
>
23
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