Figure 324. Data Clock Timing Diagram - ST STM32F423 Reference Manual

Advanced arm-based 32-bit mcus

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Serial peripheral interface/ inter-IC sound (SPI/I2S)

The order of data bits depends on LSBFIRST bit setting.

Data frame format

The SPI shift register can be set up to shift out MSB-first or LSB-first, depending on the

value of the LSBFIRST bit. Each data frame is 8 or 16 bit long depending on the size of the

data programmed using the DFF bit in the SPI_CR1 register. The selected data frame

format is applicable both for transmission and reception.

Figure 324. Data clock timing diagram

RM0430 Rev 8

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