Figure 349. Audio Sampling Frequency Definition; Figure 350. I 2 S Clock Generator Architecture - ST STM32F423 Reference Manual

Serial peripheral interface/ inter-IC sound (SPI/I2S)
When the master mode is configured, a specific action needs to be taken to properly
program the linear divider in order to communicate with the desired audio frequency.
Figure 350
system clock.
1. Where x = 2.
The audio sampling frequency may be 192 KHz, 96 kHz, 48 kHz, 44.1 kHz, 32 kHz,
22.05 kHz, 16 kHz, 11.025 kHz or 8 kHz (or any other value within this range). In order to
reach the desired frequency, the linear divider needs to be programmed according to the
formulas below:
When the master clock is generated (MCKOE in the SPIx_I2SPR register is set):
f = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD)*8)] when the channel frame is 16-bit wide
S
f = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD)*4)] when the channel frame is 32-bit wide
S
When the master clock is disabled (MCKOE bit cleared):
f = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD))] when the channel frame is 16-bit wide
S
f = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD))] when the channel frame is 32-bit wide
S
Table 176
Note: Other configurations are possible that allow optimum clock precision.
968/1324

Figure 349. Audio sampling frequency definition

presents the communication clock architecture. The I2Sx clock is always the
Figure 350. I
provides example precision values for different clock configurations.
2
S clock generator architecture
RM0430 Rev 8
RM0430