ST STM32F423 Reference Manual page 155

RM0430
Bit 20 UART5EN: UART 5 clock enable
Set and RESET by software.
0: UART 5 clock disabled
1: UART 5 clock enabled
Bit 19 UART4EN: UART 4 clock enable
Set and cleared by software.
0: UART 4 clock disabled
1: UART 4 clock enabled
Bit 18 USART3EN: USART3 clock enable
Set and cleared by software.
0: USART3 clock disabled
1: USART3 clock enabled
Bit 17 USART2EN: USART2 clock enable
Set and cleared by software.
0: USART2 clock disabled
1: USART2 clock enabled
Bit 16 Reserved, must be kept at reset value.
Bit 15 SPI3EN: SPI3 clock enable
Set and cleared by software.
0: SPI3 clock disabled
1: SPI3 clock enabled
Bit 14 SPI2EN: SPI2 clock enable
Set and cleared by software.
0: SPI2 clock disabled
1: SPI2 clock enabled
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGEN: Window watchdog clock enable
Set and cleared by software.
0: Window watchdog clock disabled
1: Window watchdog clock enabled
Bit 10 RTC APB: clock enable
Set and cleared by software.
0: RTC APB clock disabled
1: RTC APB clock enabled (default value).
Bit 9 LPTIMER1EN: LPTimer 1 clock enable
Set and reset by software.
0: LPTimer 1 clock disabled
1: LPTimer 1 clock enabled
Bit 8 TIM14EN: TIM14 reset
Set and cleared by software.
0: does not reset TIM14
1: resets TIM14
Bit 7 TIM13EN: TIM13 reset
Set and cleared by software.
0: does not reset TIM13
1: resets TIM13
Reset and clock control (RCC) for STM32F413/423
RM0430 Rev 8 155/1324
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