Nor Flash/Psram Controller; Table 43. Nor/Psram External Memory Address - ST STM32F423 Reference Manual

Flexible static memory controller (FSMC)
The HADDR[25:0] bits contain the external memory address. Since HADDR is a byte
address whereas the memory is addressed at word level, the address actually issued to the
memory varies according to the memory data width, as shown in the following table.
Memory width
8-bit
16-bit
1. In case of a 16-bit external memory width, the FSMC will internally use HADDR[25:1] to generate the
address for external memory FSMC_A[24:0].
Whatever the external memory width, FSMC_A[0] should be connected to external memory address A[0].
11.5

NOR Flash/PSRAM controller

The FSMC generates the appropriate signal timings to drive the following types of
memories:
•
Asynchronous SRAM and ROM
–
–
•
PSRAM (CellularRAM™)
–
–
–
•
NOR Flash memory
–
–
–
The FSMC outputs a unique chip select signal, NE[4:1], per bank. All the other signals
(addresses, data and control) are shared.
The FSMC supports a wide range of devices through a programmable timings among
which:
•
Programmable wait states (up to 15)
• Programmable bus turnaround cycles (up to 15)
•
Programmable output enable and write enable delays (up to 15)
• Independent read and write timings and protocol to support the widest variety of
memories and timings
•
Programmable continuous clock (FSMC_CLK) output.
The FSMC Clock (FSMC_CLK) is a submultiple of the HCLK clock. It can be delivered to the
selected external device either during synchronous accesses only or during asynchronous
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Table 43. NOR/PSRAM External memory address

(1)
Data address issued to the memory
HADDR[25:1] >> 1
8 bits
16 bits
Asynchronous mode
Burst mode for synchronous accesses
Multiplexed or non-multiplexed
Asynchronous mode
Burst mode for synchronous accesses
Multiplexed or non-multiplexed
HADDR[25:0]
RM0430 Rev 8
Maximum memory capacity (bits)
64 Mbytes x 8 = 512 Mbit
64 Mbytes/2 x 16 = 512 Mbit
RM0430