Read Interface; Relation Between Cpu Clock Frequency And Flash Memory Read Time; Table 6. Number Of Wait States According To Cpu Clock (Hclk) Frequency - ST STM32F423 Reference Manual

Embedded Flash memory interface
Block
3.4

Read interface

3.4.1

Relation between CPU clock frequency and Flash memory read time

To correctly read data from Flash memory, the number of wait states (LATENCY) must be
correctly programmed in the Flash access control register (FLASH_ACR) according to the
frequency of the CPU clock (HCLK) and the supply voltage of the device.
•
When VOS[1:0] = 0x01, the maximum value of f
•
When VOS[1:0] = 0x10, the maximum value of f
•
When VOS[1:0] = 0x11, the maximum value of f

Table 6. Number of wait states according to CPU clock (HCLK) frequency

Wait states (WS)
(LATENCY)
0 WS (1 CPU cycle)
1 WS (2 CPU cycles)
2 WS (3 CPU cycles)
3 WS (4 CPU cycles)
4 WS (5 CPU cycles)
5 WS (6 CPU cycles)
6 WS (7 CPU cycles)
After reset, the CPU clock frequency is 16 MHz and 0 wait state (WS) is configured in the
FLASH_ACR register.
It is highly recommended to use the following software sequences to tune the number of
wait states needed to access the Flash memory with the CPU frequency.
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Table 5. Flash module organization (continued)
Name
OTP area
Option bytes
Voltage range
2.7 V - 3.6 V
0 < HCLK ≤ 25
25 < HCLK ≤ 50
50 < HCLK ≤ 75
75 < HCLK ≤ 100
- 80 < HCLK ≤ 100
-
-
RM0430 Rev 8
Block base addresses
0x1FFF 7800 - 0x1FFF 7A0F
0x1FFF C000 - 0x1FFF C00F
HCLK
HCLK
HCLK
HCLK (MHz)
Voltage range Voltage range
2.4 V - 2.7 V
0 < HCLK ≤ 20 0 < HCLK ≤ 18
20 < HCLK ≤ 40 18 < HCLK ≤ 36
40 < HCLK ≤ 60 36 < HCLK ≤ 54
60 < HCLK ≤ 80 54 < HCLK ≤ 72
72 < HCLK ≤ 90
- 90 < HCLK ≤ 100
-
= 64 MHz.
= 84 MHz.
= 100 MHz.
Voltage range
2.1 V - 2.4 V 1.7 V - 2.1 V
0 < HCLK ≤ 16
16 <HCLK ≤ 32
32 < HCLK ≤ 48
48 < HCLK ≤ 64
64 < HCLK ≤ 80
80 < HCLK ≤ 96
- 96 < HCLK ≤ 100
RM0430
Size
528 byte
16 byte