Rtc Initialization And Status Register (Rtc_Isr) - ST STM32F423 Reference Manual

Real-time clock (RTC)
Bit 4 REFCKON: Reference clock detection enable (50 or 60 Hz)
Note: PREDIV_S must be 0x00FF.
Bit 3 TSEDGE: Timestamp event active edge
Bits 2:0 WUCKSEL[2:0]: Wakeup clock selection
Note: WUT = Wakeup unit counter value. WUT = (0x0000 to 0xFFFF) + 0x10000 added when
WUCKSEL[2:1 = 11].
Bits 7, 6 and 4 of this register can be written in initialization mode only (RTC_ISR/INITF = 1).
Bits 2 to 0 of this register can be written only when RTC_CR WUTE bit = 0 and RTC_ISR
WUTWF bit = 1.
It is recommended not to change the hour during the calendar hour increment as it could
mask the incrementation of the calendar hour.
ADD1H and SUB1H changes are effective in the next second.
This register is write protected. The write access procedure is described in
write protection.
25.6.4

RTC initialization and status register (RTC_ISR)

Address offset: 0x0C
Backup domain reset value: 0x0000 0007
System reset value: Not affected except INIT, INITF and RSF which are cleared to 0.
31 30 29
Res. Res. Res.
15 14 13
Res. Res TAMP1F TSOVF
rc_w0
Bits 31:17 Reserved, must be kept at reset value
Bit 16 RECALPF: Recalibration pending Flag
The RECALPF status flag is automatically set to '1' when software writes to the RTC_CALR
register, indicating that the RTC_CALR register is blocked. When the new calibration
settings are taken into account, this bit returns to '0'. Refer to
Bits 15:14 Reserved, must be kept at reset value.
764/1324
0: Reference clock detection disabled
1: Reference clock detection enabled
0: TIMESTAMP rising edge generates a timestamp event
1: TIMESTAMP falling edge generates a timestamp event
TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting
000: RTC/16 clock is selected
001: RTC/8 clock is selected
010: RTC/4 clock is selected
011: RTC/2 clock is selected
10x: ck_spre (usually 1 Hz) clock is selected
11x: ck_spre (usually 1 Hz) clock is selected and 2
(see note below)
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
TSF WUTF ALRBF ALRAF
rc_w0 rc_w0 rc_w0 rc_w0
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
INIT INITF RSF
rc_w0 rw r rc_w0
RM0430 Rev 8
16
is added to the WUT counter value
RTC register
20 19 18
Res. Res. Res.
4 3 2
INITS SHPF WUT WF ALRB WF ALRA WF
r r r
Re-calibration
RM0430
17 16
Res. RECALPF
r
1 0
r r
on-the-fly.