ST STM32F423 Reference Manual page 794

Fast-mode Plus Inter-integrated circuit (FMPI2C) interface
By default, the slave uses its clock stretching capability, which means that it stretches the
SCL signal at low level when needed, in order to perform software actions. If the master
does not support clock stretching, the FMPI2C must be configured with NOSTRETCH=1 in
the FMPI2C_CR1 register.
After receiving an ADDR interrupt, if several addresses are enabled the user must read the
ADDCODE[6:0] bits in the FMPI2C_ISR register in order to check which address matched.
DIR flag must also be checked in order to know the transfer direction.
Slave clock stretching (NOSTRETCH = 0)
In default mode, the FMPI2C slave stretches the SCL clock in the following situations:
• When the ADDR flag is set: the received address matches with one of the enabled
slave addresses. This stretch is released when the ADDR flag is cleared by software
setting the ADDRCF bit.
•
In transmission, if the previous data transmission is completed and no new data is
written in FMPI2C_TXDR register, or if the first data byte is not written when the ADDR
flag is cleared (TXE=1). This stretch is released when the data is written to the
FMPI2C_TXDR register.
• In reception when the FMPI2C_RXDR register is not read yet and a new data reception
is completed. This stretch is released when FMPI2C_RXDR is read.
•
When TCR = 1 in Slave Byte Control mode, reload mode (SBC=1 and RELOAD=1),
meaning that the last data byte has been transferred. This stretch is released when
then TCR is cleared by writing a non-zero value in the NBYTES[7:0] field.
•
After SCL falling edge detection, the FMPI2C stretches SCL low during
[(SDADEL+SCLDEL+1) x (PRESC+1) + 1] x t
Slave without clock stretching (NOSTRETCH = 1)
When NOSTRETCH = 1 in the FMPI2C_CR1 register, the FMPI2C slave does not stretch
the SCL signal.
•
The SCL clock is not stretched while the ADDR flag is set.
• In transmission, the data must be written in the FMPI2C_TXDR register before the first
SCL pulse corresponding to its transfer occurs. If not, an underrun occurs, the OVR
flag is set in the FMPI2C_ISR register and an interrupt is generated if the ERRIE bit is
set in the FMPI2C_CR1 register. The OVR flag is also set when the first data
transmission starts and the STOPF bit is still set (has not been cleared). Therefore, if
the user clears the STOPF flag of the previous transfer only after writing the first data to
be transmitted in the next transfer, he ensures that the OVR status is provided, even for
the first data to be transmitted.
•
In reception, the data must be read from the FMPI2C_RXDR register before the 9th
SCL pulse (ACK pulse) of the next data byte occurs. If not an overrun occurs, the OVR
flag is set in the FMPI2C_ISR register and an interrupt is generated if the ERRIE bit is
set in the FMPI2C_CR1 register.
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RM0430