Table 131. Dma Channel Configuration For Aes-To-Memory Data Transfer; Figure 252. Dma Transfer Of A 128-Bit Data Block During Output Phase - ST STM32F423 Reference Manual

AES hardware accelerator (AES)

Table 131. DMA channel configuration for AES-to-memory data transfer

DMA channel control
register field
Transfer size
Source burst size
(peripheral)
Destination burst size
(memory)
DMA FIFIO size
Source transfer width
(peripheral)
Destination transfer
width (memory)
Source address
increment (peripheral)
Destination address
increment (memory)

Figure 252. DMA transfer of a 128-bit data block during output phase

DMA operation in different operating modes
DMA operations are usable when Mode 1 (encryption) or Mode 3 (decryption) are selected
via the MODE[1:0] bitfield of the register AES_CR. As in Mode 2 (key derivation) the
AES_KEYRx registers must be written by software, enabling the DMA transfer through the
DMAINEN and DMAOUTEN bits of the AES_CR register have no effect in that mode.
DMA single requests are generated by AES until it is disabled. So, after the data output
phase at the end of processing of a 128-bit data block, AES switches automatically to a new
data input phase for the next data block, if any.
When the data transferring between AES and memory is managed by DMA, the CCF flag is
not relevant and can be ignored (left set) by software. It must only be cleared when
transiting back to data transferring managed by software. See
728/1324
Recommended configuration
It is the message length multiple of AES block size (4 words). According to
the case extra bytes will have to be discarded.
Single
Single
AES FIFO_size = 4 bytes
32-bit words
32-bit words
Fixed address of AES_DINR (no increment)
Yes, after each 32-bit transfer
RM0430 Rev 8
RM0430
Suspend/resume operations