Aes Key Register 3 (Aes_Keyr3); Aes Initialization Vector Register 0 (Aes_Ivr0); Aes Initialization Vector Register 1 (Aes_Ivr1) - ST STM32F423 Reference Manual

AES hardware accelerator (AES)
Bits 31:0 KEY[95:64]: Cryptographic key, bits [95:64]
Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
24.7.8

AES key register 3 (AES_KEYR3)

Address offset: 0x1C
Reset value: 0x0000 0000
31 30 29 28
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15 14 13 12
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Bits 31:0 KEY[127:96]: Cryptographic key, bits [127:96]
Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.
24.7.9

AES initialization vector register 0 (AES_IVR0)

Address offset: 0x20
Reset value: 0x0000 0000
31 30 29
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15 14 13
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Bits 31:0 IVI[31:0]: Initialization vector input, bits [31:0]
Refer to
IVI[127:0] bitfield.
The initialization vector is only used in chaining modes other than ECB.
The initialization vector may be written only when the AES peripheral is disabled.
24.7.10

AES initialization vector register 1 (AES_IVR1)

Address offset: 0x24
Reset value: 0x0000 0000
738/1324
27 26 25
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11 10 9
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28 27 26 25
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12 11 10 9
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Section 24.4.15: AES initialization vector registers on page 726
24 23 22 21
KEY[127:112]
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8 7 6 5
KEY[111:96]
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24 23 22
IVI[31:16]
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8 7 6
IVI[15:0]
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RM0430 Rev 8
20 19 18
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4 3 2
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21 20 19 18
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5 4 3 2
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for description of the
RM0430
17 16
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1 0
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17 16
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1 0
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