ST STM32F423 Reference Manual page 132

Reset and clock control (RCC) for STM32F413/423
Bit 22 PLLSRC: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source
Bits 21:18 Reserved, must be kept at reset value.
Bits 17:16 PLLP[1:0]: Main PLL (PLL) division factor for main system clock
Caution: The software has to set these bits correctly not to exceed 100 MHz on this domain.
Bits 14:6 PLLN[8:0]: Main PLL (PLL) multiplication factor for VCO
Caution: The software has to set these bits correctly to ensure that the VCO output
Note: Multiplication factors possible for VCO input frequency higher than 1 MHz but care
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Set and cleared by software to select PLL and PLLI2S clock source. This bit can be written
only when PLL and PLLI2S are disabled.
0: HSI clock selected as PLL and PLLI2S clock entry
1: HSE oscillator clock selected as PLL and PLLI2S clock entry
Set and cleared by software to control the frequency of the general PLL output clock. These
bits can be written only if PLL is disabled.
PLL output clock frequency = VCO frequency / PLLP with PLLP = 2, 4, 6, or 8
00: PLLP = 2
01: PLLP = 4
10: PLLP = 6
11: PLLP = 8
Set and cleared by software to control the multiplication factor of the VCO. These bits can
be written only when PLL is disabled. Only half-word and word accesses are allowed to
write these bits.
frequency is between 100 and 432 MHz. (check also
configuration register
VCO output frequency = VCO input frequency × PLLN with 50 ≤ PLLN ≤ 432
000000000: PLLN = 0, wrong configuration
000000001: PLLN = 1, wrong configuration
...
000110010: PLLN = 50
...
001100011: PLLN = 99
001100100: PLLN = 100
...
110110000: PLLN = 432
110110001: PLLN = 433, wrong configuration
...
111111111: PLLN = 511, wrong configuration
must be taken to fulfill the VCO output frequency range as specified above.
(RCC_PLLI2SCFGR))
RM0430 Rev 8
RM0430
Section 6.3.26: RCC PLLI2S