ST STM32F423 Reference Manual page 164

Reset and clock control (RCC) for STM32F413/423
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 QSPILPEN: QUADSPI memory controller module clock enable during Sleep mode
Bit 0 FSMCLPEN: Flexible memory controller module clock enable during Sleep mode
164/1324
Set and cleared by software.
0: QUADSPI module clock disabled during Sleep mode
1: QUADSPI module clock enabled during Sleep mode
Set and cleared by software.
0: FSMC clock disabled during Sleep mode
1: FSMC clock enabled during Sleep mode
RM0430 Rev 8
RM0430