Dfsdm Channel Y Watchdog Filter Data Register (Dfsdm_Chywdatr) - ST STM32F423 Reference Manual

Advanced arm-based 32-bit mcus

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Digital filter for sigma delta modulators (DFSDM)

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:22 AWFORD[1:0]: Analog watchdog Sinc filter order on channel y

0: FastSinc filter type

filter type transfer function:

FastSinc filter type transfer function:

This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).

Bit 21 Reserved, must be kept at reset value.

Bits 20:16 AWFOSR[4:0]: Analog watchdog filter oversampling ratio (decimation rate) on channel y

0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is

also the decimation ratio of the analog data rate.

This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).

Note: If AWFOSR = 0 then the filter has no effect (filter bypass).

Bits 15:12 BKSCD[3:0]: Break signal assignment for short-circuit detector on channel y

BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y

BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y

Bits 11:8 Reserved, must be kept at reset value.

Bits 7:0 SCDT[7:0]: short-circuit detector threshold for channel y

These bits are written by software to define the threshold counter for the short-circuit detector. If this

value is reached, then a short-circuit detector event occurs on a given channel.

DFSDM channel y watchdog filter data register

(DFSDM_CHyWDATR)

This register contains the data resulting from the analog watchdog filter associated to the

input channel y.

Address offset: 0x0C + 0x20 * y, (y = 0 to 7)

Reset value: 0x0000 0000

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RM0430 Rev 8

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