Lptim Control Register (Lptim_Cr) - ST STM32F423 Reference Manual

Low-power timer (LPTIM)
Bits 4:3 CKFLT[1:0]: Configurable digital filter for external clock
The CKFLT value sets the number of consecutive equal samples that should be detected when a
level change occurs on an external clock signal before it is considered as a valid level transition. An
internal clock source must be present to use this feature
00: any external clock signal level change is considered as a valid transition
01: external clock signal level change must be stable for at least 2 clock periods before it is
considered as valid transition.
10: external clock signal level change must be stable for at least 4 clock periods before it is
considered as valid transition.
11: external clock signal level change must be stable for at least 8 clock periods before it is
considered as valid transition.
Bits 2:1 CKPOL[1:0]: Clock Polarity
If LPTIM is clocked by an external clock source:
When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active
edge or edges used by the counter:
00: the rising edge is the active edge used for counting
01: the falling edge is the active edge used for counting
10: both edges are active edges. When both external clock signal edges are considered active
ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at
least four time the external clock frequency.
11: not allowed
If the LPTIM is configured in Encoder mode (ENC bit is set):
00: the encoder sub-mode 1 is active
01: the encoder sub-mode 2 is active
10: the encoder sub-mode 3 is active
Refer to Section 21.4.14: Encoder mode
Bit 0 CKSEL: Clock selector
The CKSEL bit selects which clock source the LPTIM will use:
0: LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)
1: LPTIM is clocked by an external clock source through the LPTIM external Input1
Caution: The LPTIM_CFGR register must only be modified when the LPTIM is disabled (ENABLE bit
reset to '0').
21.6.5

LPTIM control register (LPTIM_CR)

Address offset: 0x010
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
672/1324
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
for more details about Encoder mode sub-modes.
24 23 22
Res. Res. Res.
8 7 6
Res. Res. Res.
RM0430 Rev 8
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
CNT
Res. Res. Res.
STRT
rw
RM0430
17 16
Res. Res.
1 0
SNG ENA
STRT BLE
rw rw