Aes Error Management; Aes Interrupts; Figure 253. Aes Interrupt Signal Generation - ST STM32F423 Reference Manual

RM0430
in ECB/CBC modes
24.4.17

AES error management

The read error flag (RDERR) and write error flag (WRERR) of the AES_SR register are set
when an unexpected read or write operation, respectively, is detected. An interrupt can be
generated if the error interrupt enable (ERRIE) bit of the AES_CR register is set. For more
details, refer to
Note: AES is not disabled after an error detection and continues processing.
AES can be re-initialized at any moment by clearing then setting the EN bit of the AES_CR
register.
Read error flag (RDERR)
When an unexpected read operation is detected during the computation phase or during the
input phase, the AES read error flag (RDERR) is set in the AES_SR register. An interrupt is
generated if the ERRIE bit of the AES_CR register is set.
The RDERR flag is cleared by setting the corresponding ERRC bit of the AES_CR register.
Write error flag (WDERR)
When an unexpected write operation is detected during the computation phase or during the
output phase, the AES write error flag (WRERR) is set in the AES_SR register. An interrupt
is generated if the ERRIE bit of the AES_CR register is set.
The WDERR flag is cleared by setting the corresponding ERRC bit of the AES_CR register.
24.5

AES interrupts

There are three individual maskable interrupt sources generated by the AES peripheral, to
signal the following events:
•
computation completed
•
read error, see
•
write error, see
These three sources are combined into a common interrupt signal aes_it that connects to
NVIC (nested vectored interrupt controller).
Each AES interrupt source can individually be enabled/disabled, by setting/clearing the
corresponding enable bit of the AES_CR register. See
in Section 24.4.8: AES basic chaining modes (ECB, CBC)
Section 24.5: AES interrupts.
Section 24.4.17
Section 24.4.17

Figure 253. AES interrupt signal generation

RM0430 Rev 8
AES hardware accelerator (AES)
Figure 253.
as example.
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