I 2 C Fltr Register (I2C_Fltr) - ST STM32F423 Reference Manual

RM0430
2
27.6.10 I C FLTR register (I2C_FLTR)
Address offset: 0x24
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:5 Reserved, must be kept at reset value
Bit 4 ANOFF: Analog noise filter OFF
Note: ANOFF must be configured only when the I2C is disabled (PE = 0).
Bits 3:0 DNF[3:0]: Digital noise filter
These bits are used to configure the digital noise filter on SDA and SCL inputs. The digital filter
will suppress the spikes with a length of up to DNF[3:0] * TPCLK1.
Note: DNF[3:0] must be configured only when the I2C is disabled (PE = 0). If the analog filter
12 11 10 9
Res. Res. Res.
0: Analog noise filter enable
1: Analog noise filter disable
0000: Digital noise filter disable
0001: Digital noise filter enabled and filtering capability up to 1* TPCLK1.
...
1111: Digital noise filter enabled and filtering capability up to 15* TPCLK1.
is also enabled, the digital filter is added to the analog filter.
Inter-integrated circuit (I
8 7 6
Res. Res. Res.
RM0430 Rev 8
5 4 3 2
Res. ANOFF DNF[3:0]
rw rw rw
2
C) interface
1 0
rw rw
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